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Table 3. Statistics on the self-test program Test application TPG*

in Embedded Hardware and Software Self-Testing Methodologies for Processor Cores
by Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Chen 2000
"... In PAGE 5: ... We expect them to be tested intensively during the test for the targeted components. Table3 shows the statistics on various programs contained in the software tester, including the test pattern generation program and the test application programs for ALU, SHU, and PC. For each program, we show the number of instructions included in the program, the size of the program in bytes, and the execution time in the number of processor cycles.... ..."
Cited by 4

Table 3. Statistics on the self-test program Test application TPG*

in Embedded Hardware and Software Self-Testing Methodologies for Processor Cores
by Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Chen 2000
"... In PAGE 5: ... We expect them to be tested intensively during the test for the targeted components. Table3 shows the statistics on various programs contained in the software tester, including the test pattern generation program and the test application programs for ALU, SHU, and PC. For each program, we show the number of instructions included in the program, the size of the program in bytes, and the execution time in the number of processor cycles.... ..."
Cited by 4

Table 4: Test pattern generation coverage

in Generating Test Patterns for Bridge Faults in CMOS ICs
by Brian Chess Tracy, Alvin Jee, Haluk Konuk, Rich Mcgowen, M. Abramovici, J. M. Acken
"... In PAGE 2: ... This means that there are a signi#0Ccantnumber of faults that can never be tested with the discrepancy placed on the back wire. Table4 shows the number of bridge faults covered, proved untestable, or aborted by our system. For the ten circuits, wecover an average of 99.... In PAGE 2: ... We fail to generate tests for or proveuntestable very few of the faults. Table4 also shows the time in seconds on a Digital Equipment Corporation Alpha... ..."

Table 2. Functional test pattern generation.

in Functional test generation for behaviorally sequential models
by F. Ferrandi, G. Ferrara, D. Sciuto 2001
Cited by 11

Table 2. Functional test pattern generation.

in Functional Test Generation for Behaviorally Sequential Models
by G. Ferrara, G. Ferrara, D. Sciuto, A. Fin, F. Fummi 2001
Cited by 11

TABLE I TEST PATTERN GENERATION FOR BENCHMARK CIRCUITS

in Bridging fault testability of BDD circuits
by Junhao Shi, Görschwin Fey, Rolf Drechsler 2005
Cited by 1

Table 2. Behavioral test pattern generation.

in Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels
by M. Bacis, G. Buonanno, F. Ferrandi, F. Fummi, L. Gerli, D. Sciuto

Table 4: Test pattern generation bridge fault statistics References

in Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
by Joel Ferguson, Tracy Larrabee 1991
"... In PAGE 5: ... For com- parison, the results do not include global implications (learning). Table4 shows the performance of the system when generating test patterns for all realistic bridge faults. The second row gives the number of realistic bridge faults in the circuit, the next line gives the number of faults pruned from the faultlist due to feedback, fol- lowed by four lines giving the number of faults that Nemesis proved untestable, failed on due to excessive backtrack and generated a test for.... ..."
Cited by 41

Table 4: Results for Redundancy Removal and Test Pattern Generation.

in Testing Core-Based Digital Systems: A Symbolic Methodology
by F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto 1997
"... In PAGE 17: ... Redundancy removal can be applied at rst to pairs of interconnected modules to improve the testability. The SEL, ANA, and STORE modules are therefore simpli ed, as shown in the second and third columns of Table4 . It is interesting to notice that the BDD description of the core is su cient to identify redundant faults in the interconnected module (ANA).... In PAGE 17: ... No other knowledge of its internal structure is necessary. Test generation is then applied to a module at a time by achieving the testability results reported in Table4 . For this operation, the functional description of the core allows to backward and forward propagate the test sequences of the other modules.... ..."
Cited by 2

Table 1: True-Time Test Pattern Generation Results

in WHAT IS TRUE-TIME DELAY TEST?
by Failure Patterns, In Ic’s Page, F. Barnhart 2004
"... In PAGE 7: ... Path Delay Tests are generally considered to be a characterization test as opposed to detecting defects, and are not normally fault simulated. RESULTS In Table1 below are some recent results for some ASICs from the IBM ASIC foundry in Burlington, Vermont. The sizes ranged from 2 to 8 million gates (one hundred thousand to almost eight hundred thousand scan elements), and all chips used our OPMISR compression.... In PAGE 19: ...Table1 summarizes the assumptions used in this modeling exercise. A key input to the model is the delay defect percentage, set at 20 percent in this example.... In PAGE 19: ...50 *Dev cost CoQ 26.4 $ / def Table1 : Economic model assumptions Figure 2: Test data volume with delay test and compression 0 20,000 40,000 60,000 80,000 100,000 No delay No comp Delay OPMISR Delay OPMISR+ Delay No comp Mbit 0.00 0.... ..."
Results 1 - 10 of 99,772