Results 1 - 10 of 106,105

Test pattern generation using Boolean satisfiability

by Tracy Larrabee - IEEE Transactions on Computer-Aided Design , 1992
"... Abstract-This article describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean diference between the unfaulted and faulted ..."
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Abstract-This article describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean diference between the unfaulted

Diagnostic Test Pattern Generation . . .

by Yu Zhang , 2012
"... In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good for failure diagnosis. Physical defects in circuits are modeled by different Fault Models to facilitat ..."
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In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good for failure diagnosis. Physical defects in circuits are modeled by different Fault Models

Sequential Automatic Test Pattern Generation

by Constraint Programming Sebastian, Sebastian Brand
"... The problem of automatic test pattern generation for sequential digital circuits is considered from the point of view of constraint programming. ..."
Abstract - Cited by 3 (1 self) - Add to MetaCart
The problem of automatic test pattern generation for sequential digital circuits is considered from the point of view of constraint programming.

Test Pattern Generator

by L. Guiller, C. Landrault, S. Pravossoudovitch, H. J. Wunderlich, L. Guiller, C. Landrault, S. Pravossoudovitch, H. J. Wunderlich , 2001
"... Abstract: In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. N ..."
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Abstract: In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG

Automatic Test Pattern Generation

by unknown authors
"... The complexity of VLSI devices increases rapidly as technology increases, resulting in an increase in the difficulty of test generation. Traditional test generation algorithms target one fault of a fault set at a time to generate a test. This paper presents a brief overview of a few different approa ..."
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The complexity of VLSI devices increases rapidly as technology increases, resulting in an increase in the difficulty of test generation. Traditional test generation algorithms target one fault of a fault set at a time to generate a test. This paper presents a brief overview of a few different

Antirandom test patterns generation tool

by Huifang Yin, Huifang Yin , 1996
"... Random testing is a well known concept that each test is selected randomly regardless of the test previously applied. This paper introduces the antirandom testing which each test applied is chosen such that its total distance from all previous tests is maximum. And one automatic test patterns genera ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
generation tool using this concept is implemented. At the same time, one popular test generation and simulation tool Nemesis is used to simulate the test patterns generated from Random testing, Antirandom testing and Nemesis which used the Boolean satis ability method, by comparing their fault coverage

Techniques for SAT-Based Constrained Test Pattern Generation

by Jiří Balcárek, Petr Fišer, Jan Schmidt - 14TH EUROMICRO CONFERENCE ON DIGITAL SYSTEMS DESIGN , 2011
"... Abstract—Testing of digital circuits seems to be a completely mastered part of the design flow, but constrained test patterns generation is still a highly evolving branch of digital circuit testing. Our previous research on constrained test pattern generation proved that we can benefit from an imp ..."
Abstract - Cited by 7 (6 self) - Add to MetaCart
Abstract—Testing of digital circuits seems to be a completely mastered part of the design flow, but constrained test patterns generation is still a highly evolving branch of digital circuit testing. Our previous research on constrained test pattern generation proved that we can benefit from

Comparative Power Analysis of LFSR Test Pattern Generators

by H. Srikanth Kamath, Srivastava Saket Garg
"... Automatic Test Pattern Generation Automatic Test Pattern Generator is an electronic de-sign automation method used to find an input sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior c ..."
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Automatic Test Pattern Generation Automatic Test Pattern Generator is an electronic de-sign automation method used to find an input sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior

Synthesis of Efficient Linear Test Pattern Generators

by Avijit Dutta, Nur A. Touba
"... This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area, speed, internal fanout, and randomness properties and outperform existing linear test pattern generator designs includin ..."
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This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area, speed, internal fanout, and randomness properties and outperform existing linear test pattern generator designs

New Techniques for Deterministic Test Pattern Generation

by Ilker Hamzaoglu, Janak H. Patel - Journal of Electronic Testing: Theory and Applications , 1999
"... This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting co ..."
Abstract - Cited by 55 (3 self) - Add to MetaCart
This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting
Results 1 - 10 of 106,105