Results

**1 - 8**of**8**### Table 2: Results of Technology-Independent Synthesis Design Original resyn2 resyn2rs Runtime, sec

"... In PAGE 5: ... Reference Results In this section we apply ABC to the hierarchical designs produced by Quartus II. Table2 shows the results of technology-independent synthesis and the runtimes. Table 3 shows the results of technology mapping while Table 4 shows the outcome of applying the experiment flow in Figure 4 to design ava.... In PAGE 5: ... Table 3 shows the results of technology mapping while Table 4 shows the outcome of applying the experiment flow in Figure 4 to design ava. In Table2 , column Name lists the benchmark name. Columns Lev and Node show the number of logic levels and nodes in the AIG.... In PAGE 5: ... Columns Lev and Node show the number of logic levels and nodes in the AIG. The first section of Table2 characterizes the original network: The next two sections show the results of AIG rewriting using script resyn2 [23] followed by script resyn2rs [22]. In the last section of Table 2, column read is runtime of reading the hierarchical BLIF and converting it into an AIG by structural hashing.... In PAGE 5: ... The first section of Table 2 characterizes the original network: The next two sections show the results of AIG rewriting using script resyn2 [23] followed by script resyn2rs [22]. In the last section of Table2 , column read is runtime of reading the hierarchical BLIF and converting it into an AIG by structural hashing. Columns res2 and res2rs are the runtimes of scripts resyn2 and resyn2rs .... In PAGE 6: ... Versions -0 , -1 , and -2 of the designs are written by Quartus before technology-independent synthesis, before technology mapping and after technology mapping into 4-LUTs, respectively. All these versions were optimized in ABC by applying script resyn2 followed by resyn2rs as shown in Table2 . Finally, version -3 is the same as version - 2 without optimization in ABC.... ..."

### Table 2. The results of MIS-pga(delay) are cited from[14] (since we are unable to run their program directly). We obtain the results of Flow-Map by first synthesizing the original benchmarks using a standard MIS optimization script (used by Chortle-crf [8] and DAG-Map [2]) for technology-independent optimization, then applying the Flow-Map algorithm for technology mapping. Since MIS-pga(delay) combines logic synthesis and technology

in An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs

"... In PAGE 6: ...8% +7.1% 1 1 a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0 a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a1a0a2a0a1a0a1a0a1a0a1a0a1a0a1a0 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 a3 Table2 Comparison with MIS-pga (delay optimization) algorithm. mapping, in several cases it produced mapping solutions of smaller depth than those of Flow-Map.... ..."

### Table 4 illustrates the use of AnSER to guide the local rewriting implementation in the ABC logic synthesis pack- age [1]. AnSER calculates the global reliability impact of each local change to decide whether to accept this change. After checking hundreds of circuit rewriting possibilities, those that improve SER and have limited area overhead are retained. The data indicate that, on average, SER decreases by 10;7%, while area decreases by 2:3%. For instance, for alu4, a circuit with 740 gates, we achieve 29% lower SER, while reducing area by 0:5%. Although area optimization is often thought to hurt reliability, results show that carefully guided logic transformations can eliminate this problem.

"... In PAGE 6: ... Table4 : Improvements in SER and area with local rewriting. 7 Conclusions We have presented a technology-independent reliability evaluator AnSER designed for use in logic synthesis.... ..."

### Table 1: Multi-level benchmarks: number of literals in factored form

"... In PAGE 16: ... The following tools were used for generating the layouts: the GORDIAN package for placement [14], the TIMBERWOLF global router [15], and the YACR detailed router [21]. Table1 goes here. In both cases, the technology-independent optimizations were performed using the MIS pro- gram.... ..."

### Table 2: Gate reductions and performance of the ODC merging algorithm on unoptimized benchmarks. The algorithm has a timeout of 5000 seconds and is denoted by U. benchmarks #gates time(s) #merge %area reduct

"... In PAGE 12: ...1 ODC Equivalence Results In this section, we present results from a variety of benchmarks that indicate the existence of several merging opportunities due to ODCs leading to a reduction in circuit size. Table2 shows the results of applying our ODC merging algorithm on unoptimized benchmarks. The timeout was set for 5000 seconds.... In PAGE 13: ... The last columns show the improvement achieved by doing ODC merging on the optimized design. The results indicate similar reductions and times to Table2 and that the optimiza- tions done to construct FRAIGs are orthogonal to the ones done here. Also, performing ODC merging on an AIG network results in only a minor increase in gate reduction over the results in Table 2.... In PAGE 13: ... The results indicate similar reductions and times to Table 2 and that the optimiza- tions done to construct FRAIGs are orthogonal to the ones done here. Also, performing ODC merging on an AIG network results in only a minor increase in gate reduction over the results in Table2 . This shows that we do not require a technology-independent representation like FRAIGs to nd several node mergers.... ..."

Cited by 2

### Table 4: Results for Quartus II and ABC on Design ava Synthesis

"... In PAGE 5: ... Table 2 shows the results of technology-independent synthesis and the runtimes. Table 3 shows the results of technology mapping while Table4 shows the outcome of applying the experiment flow in Figure 4 to design ava. In Table 2, column Name lists the benchmark name.... In PAGE 6: ... Table4 shows the effect that different synthesis tools have on the placed and routed design by using the experiment flow illustrated in Figure 4. The chosen ... In PAGE 7: ... The clock constraint was arbitrarily set to 20ns for both netlists. Figure 5: Slack Histogram for QIS Figure 6: Slack Histogram for ABC This can be explained with the higher number of worst case logic levels in the ABC generated netlist in comparison to the QIS generated netlist as shown in Table4 . In fact, the ABC generated netlist has 136 paths with 47 logic levels while the QIS generated netlist has only 72 paths with 29 logic levels.... ..."

### Table 3: Minimal express interval and corresponding minimal network size for hierarchical tori, in the form of a3 va25 Nmina5 .

2005

"... In PAGE 4: ... In order for a hierar- chical torus to save energy, the following inequality must hold ER9 a29 N 2v a4 v 2 a31 a26 ER5 a6 N 2 a21 Na3 vER5 a18 ER9a5 a16 v2ER9 which is equivalent to v a16 ER9 ER5 (4) N a16 v2ER9 vER5 a18 ER9 (5) Inequality (4) determines the minimal express interval for a hier- archical torus to achieve better energy efficiency than a 2-D torus, and inequality (5) determines the minimal network size for a certain express interval. Table3 lists the minimal express interval and corre- sponding minimal network size in the form of a3 va25 Nmina5 . Table 3: Minimal express interval and corresponding minimal network size for hierarchical tori, in the form of a3 va25 Nmina5 .... In PAGE 4: ... Note that the optimal express interval is technology-independent. Table3 and 4 show similar trends to those for high-dimensional tori. Linear load, larger buffer size and technology progress all make networks more likely to benefit from topology improvements, but technology progress also makes networks more sensitive to workload.... In PAGE 5: ... For hierarchical tori and express cubes, ER9 ER5 is also the minimal express interval. From Table3 and 5, the minimal express interval switches between 2 and 3 at 35nm technology for different load mod- els, so which topology is better depends on which load model is closer to reality. 4.... ..."

Cited by 12

### Table 2: Performance and transistor count of Alpha microprocessors. Spec95 results #28cint95, cfp95#29

"... In PAGE 11: ....5MB of level-2 cache, memory controller and directory protocol support, all integrated into a single die. The con#0Cgurations of processors and caches in the CMP nodes are motivated by the tradeo#0B between processor design complexity and performance discussed in Section 1. The actual parameters used to de#0Cne the organization of these nodes are based on a case study of the area#2Fperformance tradeo#0B between two microprocessors from the Alpha family #28 Table2 #29. This case is presented in the remaining of this section.... In PAGE 11: ... This case is presented in the remaining of this section. Table2 presents a comparison of the area and performance characteristics of the 21064 and 21264 designs. The number of transistors #5B9, 10#5D is used as a technology-independent estimate of die area; Spec95 results #5B33#5D are used as performance metrics.... In PAGE 12: ...ILP-enhanced design if fabricated under the same technology 1 . The normalized indices #28with respect to the 21064 processor, Table2 #29 account for clock speed di#0Berences to yield an estimate of the relative performance between the two microprocessors under the assumption of same fabrication technology. By factoring out clock speeds, the normalized performance numbers provide an approximation to the speedup due to architectural enhancements.... In PAGE 12: ... By factoring out clock speeds, the normalized performance numbers provide an approximation to the speedup due to architectural enhancements. The data in Table2 show that a nine-fold increase in transistor count results in three-fold #28normalized#29 speedups due to architectural enhancements. In other words, the same transistor budget of the high- performance processor can be used to design nine simpler engines with a third of the performance, under the assumption of equal clock speed.... ..."

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