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SYSTOLIC ARITHMETIC ARCHITECTURES
"... Abstract:- In this paper parallel-ism on che algorithmic, architec-tural, and arithmetic levels is exploited in the design of a Residue Number System (RNS) based archite:;ture. The architecture is basecl on modulo processors. Each modulo processor is imple-mented 1:)y two dimensional systol-ic arr,: ..."
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Abstract:- In this paper parallel-ism on che algorithmic, architec-tural, and arithmetic levels is exploited in the design of a Residue Number System (RNS) based archite:;ture. The architecture is basecl on modulo processors. Each modulo processor is imple-mented 1:)y two dimensional systol-ic arr
An efficient algorithm for exploiting multiple arithmetic units
- IBM JOURNAL OF RESEARCH AND DEVELOPMENT
, 1967
"... This paper describes the methods employed in the floating-point area of the System/360 Model 91 to exploit the existence of multiple execution units. Basic to these techniques is a simple common data busing and register tagging scheme which permits simultaneous execution of independent instructions ..."
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Cited by 391 (1 self)
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optimizes the program execution on a local basis. The application of these techniques is not limited to floating-point arithmetic or System/360 architecture. It may be used in almost any computer having multiple execution units and one or more 'accumulators.' Both of the execution units, as well
Why systolic architectures
- IEEE Computer
, 1982
"... Systolic architectures, which permit multiple computations for each memory access, can speed execution of ..."
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Cited by 280 (6 self)
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Systolic architectures, which permit multiple computations for each memory access, can speed execution of
Some efficient solutions to the affine scheduling problem -- Part I One-dimensional Time
, 1996
"... Programs and systems of recurrence equations may be represented as sets of actions which are to be executed subject to precedence constraints. In many cases, actions may be labelled by integral vectors in some iteration domain, and precedence constraints may be described by affine relations. A s ..."
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Cited by 266 (22 self)
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schedule for such a program is a function which assigns an execution date to each action. Knowledge of such a schedule allows one to estimate the intrinsic degree of parallelism of the program and to compile a parallel version for multiprocessor architectures or systolic arrays. This paper deals
A Systolic VLSI Architecture for Complex SVD
- PROC. OF THE IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
, 1991
"... This thesis presents a systolic algorithm for the SVD of arbitrary complex matrices, based on the cyclic Jacobi method with "parallel ordering". As a basic step in the algorithm, a two-step, two-sided unitary transformation scheme is employed to diagonalize a complex 2 x 2 matrix. The tran ..."
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Cited by 13 (1 self)
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This thesis presents a systolic algorithm for the SVD of arbitrary complex matrices, based on the cyclic Jacobi method with "parallel ordering". As a basic step in the algorithm, a two-step, two-sided unitary transformation scheme is employed to diagonalize a complex 2 x 2 matrix
Concurrent Error Detection in Finite Field Arithmetic Operations using Pipelined and Systolic Architectures
, 2007
"... In this work we consider mainly detection of errors in polynomial, dual and normal bases arith-metic operations. Error detection is performed by recomputing with shifted operands method while the operation unit is in use. This scheme is efficient for pipelined architectures, particularly systolic ar ..."
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Cited by 1 (0 self)
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In this work we consider mainly detection of errors in polynomial, dual and normal bases arith-metic operations. Error detection is performed by recomputing with shifted operands method while the operation unit is in use. This scheme is efficient for pipelined architectures, particularly systolic
A decision procedure for bit-vectors and arrays
- IN COMPUTER AIDED VERIFICATION, NUMBER 4590 IN LNCS
, 2007
"... STP is a decision procedure for the satisfiability of quantifier-free formulas in the theory of bit-vectors and arrays that has been optimized for large problems encountered in software analysis applications. The basic architecture of the procedure consists of word-level pre-processing algorithms fo ..."
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Cited by 190 (11 self)
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STP is a decision procedure for the satisfiability of quantifier-free formulas in the theory of bit-vectors and arrays that has been optimized for large problems encountered in software analysis applications. The basic architecture of the procedure consists of word-level pre-processing algorithms
A Bandwidth-Efficient Architecture for Media Processing
- In 31st International Symposium on Microarchitecture
, 1998
"... Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are poorly matched to conventional microprocessor architectures, they are a good fit for modern VLSI technology with its high ..."
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Cited by 141 (16 self)
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arithmetic capacity but limited global bandwidth. The stream programming model, in which an application is coded as streams of data records passing through computation kernels, exposes both parallelism and locality in media applications that can be exploited by VLSI architectures. The Imagine architecture
High-Speed Systolic Architectures for Finite Field Inversion and Division ∗
"... Based on a new reformulation of the extended Euclidean al-gorithm, systolic architectures suitable for VLSI implemen-tations are proposed for finite field inversion and division in this paper. The architectures proposed in this paper can achieve O(m2) area-time complexity, O(m) latency, and crit-ica ..."
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Cited by 1 (0 self)
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Based on a new reformulation of the extended Euclidean al-gorithm, systolic architectures suitable for VLSI implemen-tations are proposed for finite field inversion and division in this paper. The architectures proposed in this paper can achieve O(m2) area-time complexity, O(m) latency, and crit
systolic architecture for LMS adaptive filtering with minimal adaption delay
- in Proceedings of 9 th International Conference on VLSI Design
, 1996
"... Existing systolic architectures for the LMS algo-rithm with delayed coeficient adaptation have large adaptation delay and hence degraded convergence be-haviour. This paper presents a systolic architecture with minimal adaptation delay and input/output la-tency, thereby improving the convergence beh ..."
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Cited by 6 (1 self)
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behaviour to near that of the original LMS algorithm. T h e architec-ture is synthesized by using a number of b n c t i o n pre-serving transformations o n the signal flow graph repre-sentation of the delayed LMS algorithm. With the use of carry-save arithmetic, the systolic folded pipelined architecture
Results 1 - 10
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1,978
