"... In PAGE 23: ... For the SVC, an access is counted as a miss if data is supplied by the next level memory; data transfers between the L1 caches are not counted as misses. Table3 presents the bus utilization for the SVC. From these preliminary experiments, we make three observations: (i) the hit latency of data memory significantly affects ARB performance, (ii) the SVC trades-off hit rate for hit latency and the ARB trades-off hit latency for hit rate to achieve performance, and (iii) for the same total data storage, the SVC performs better than a contention-free ARB having a hit latency of 3 or more cycles.... ..."

"... In PAGE 23: ... For the SVC, an access is counted as a miss if data is supplied by the next level memory; data transfers between the L1 caches are not counted as misses. Table3 presents the bus utilization for the SVC. From these preliminary experiments, we make three observations: (i) the hit latency of data memory significantly affects ARB performance, (ii) the SVC trades-off hit rate for hit latency and the ARB trades-off hit latency for hit rate to achieve per- formance, and (iii) for the same total data storage, the SVC performs better than a contention-free ARB having a hit latency of 3 or more cycles.... ..."

"... In PAGE 13: ...2 Baseline SVC Performance The performance of the baseline SVC design described in Section 3.1 is summarized in Table3 . We see that this baseline implementation produces moderate speed-ups for Go, M88Ksim,andWordcount.... ..."

"... In PAGE 14: ...2 Baseline SVC Performance The performance of the baseline SVC design described in Section 3.1 is summarized in Table3 . We see that this baseline implementation produces moderate speed-ups for Go, M88Ksim, and Wordcount.... ..."

"... In PAGE 13: ...2 Baseline SVC Performance The performance of the baseline SVC design described in Section 3.1 is summarized in Table3 . We see that this baseline implementation produces moderate speed-ups for Go, M88Ksim, and Wordcount.... ..."

"... In PAGE 13: ...2 Baseline SVC Performance The performance of the baseline SVC design described in Section 3.1 is summarized in Table3 . We see that this baseline implementation produces moderate speed-ups for Go, M88Ksim,andWordcount.... ..."

"... In PAGE 23: ... The configurations keep total data storage of the SVC and ARB/cache storage roughly the same, since the amount of ARB storage is rather modest compared to its data cache. The miss rates for the ARB and the SVC for a total storage of 32KB are shown in Table2 . For the SVC, an access is counted as a miss if data is supplied by the next level memory; data transfers between the L1 caches are not counted as misses.... ..."

"... In PAGE 23: ... The configurationskeep total data storage of the SVC and ARB/cache storage roughlythe same, since the amount of ARB storage is rather modest compared to its data cache. The miss rates for the ARB and the SVC for a total storage of 32KB are shown in Table2 . For the SVC, an access is counted as a miss if data is supplied by the next level memory; data transfers between the L1 caches are not counted as misses.... ..."

"... In PAGE 4: ... Like mode transition tables, event tables make explicit only those events that cause the variable defined by the table to change. Table4 is also an event table. It describes the controlled variable SvcLight as a function of the current mode and the variables SvcReset and SvcMiles.... ..."

"... In PAGE 2: ... All are academic teams from nine di erent countries (Australia, China, France, Germany, Korea, Sin- gapore, Spain, Turkey, and United States). Table1 shows all the participating teams, with nine decided to remain anonymous after the results were announced. Team 19 submitted three separate programs for each task based on di erent al- gorithms.... ..."