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Complexity-effective superscalar processors

by Subbarao Palacharla, J. E. Smith, et al. - IN PROCEEDINGS OF THE 24TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE , 1997
"... The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are ana-lyzed. Each is modeled and Spice simulated for ..."
Abstract - Cited by 467 (5 self) - Add to MetaCart
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are ana-lyzed. Each is modeled and Spice simulated

Quantifying the Complexity of Superscalar Processors.

by Subbarao Palacharla , Norman P Jouppi , James E Smith , 1996
"... Abstract To characterize future performance limitations of superscalar processors, the delays of key pipeline structures in superscalar processors are studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection log ..."
Abstract - Cited by 85 (0 self) - Add to MetaCart
Abstract To characterize future performance limitations of superscalar processors, the delays of key pipeline structures in superscalar processors are studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection

The Microarchitecture of Superscalar Processors

by James E. Smith, Gurindar S. Sohi , 1995
"... Superscalar processing is the latest in a long series of innovations aimed at producing ever-faster microprocessors. By exploiting instruction-level parallelism, superscalar processors are capable of executing more than one instruction in a clock cycle. This paper discusses the microarchitecture of ..."
Abstract - Cited by 99 (1 self) - Add to MetaCart
Superscalar processing is the latest in a long series of innovations aimed at producing ever-faster microprocessors. By exploiting instruction-level parallelism, superscalar processors are capable of executing more than one instruction in a clock cycle. This paper discusses the microarchitecture

Quantifying the Complexity of Superscalar Processors

by Subbarao Palacharlay, James E. Smith
"... To characterize future performance limitations of superscalar processors, the delays of key pipeline structures in superscalar processors are studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and op ..."
Abstract - Add to MetaCart
To characterize future performance limitations of superscalar processors, the delays of key pipeline structures in superscalar processors are studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic

Data Caches for Superscalar Processors

by Toni Juan, Juan J. Navarro, Olivier Temam - In International Conference on Supercomputing , 1997
"... As the number of instructions executed in parallel increases, superscalar processors will require higher bandwidth from data caches. Because of the very high cost of true multi-ported caches, alternative cache designs must be evaluated. The purpose of this study is to examine the data cache bandwidt ..."
Abstract - Cited by 16 (1 self) - Add to MetaCart
As the number of instructions executed in parallel increases, superscalar processors will require higher bandwidth from data caches. Because of the very high cost of true multi-ported caches, alternative cache designs must be evaluated. The purpose of this study is to examine the data cache

Probabilistic Scoreboards for Superscalar Processors

by Bjarne Steensgaard, Bjarne Steensgaard , 1995
"... A tool often used by instruction schedulers for VLIW processors is a resource matrix. The resource matrix can be used to exactly model which functional units is utilized in which cycles during execution of the scheduled instructions. The resource matrix cannot model the behavior of a superscalar pro ..."
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A tool often used by instruction schedulers for VLIW processors is a resource matrix. The resource matrix can be used to exactly model which functional units is utilized in which cycles during execution of the scheduled instructions. The resource matrix cannot model the behavior of a superscalar

Performance Measures of Superscalar Processor

by K. A. Parthasarathy
"... In this paper the author describes about superscalar processor and its architecture. A superscalar architecture is one in which several instructions can be initiated simultaneously and executed independently. pipelining allows several instructions to be executed at the same time, but they have to be ..."
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In this paper the author describes about superscalar processor and its architecture. A superscalar architecture is one in which several instructions can be initiated simultaneously and executed independently. pipelining allows several instructions to be executed at the same time, but they have

Performance Factors For Superscalar Processors

by James Bennett, James E. Bennett, James E. Bennett, Michael J. Flynn, Michael J. Flynn, Michael J. Flynn , 1995
"... This paper introduces three performance factors for dynamically scheduled superscalar processors. These factors, availability, efficiency, and utility, are then used to explain the variations in performance that occur with different processor and memory system features. The processor features that a ..."
Abstract - Cited by 23 (2 self) - Add to MetaCart
This paper introduces three performance factors for dynamically scheduled superscalar processors. These factors, availability, efficiency, and utility, are then used to explain the variations in performance that occur with different processor and memory system features. The processor features

Performance Factors For Superscalar Processors

by James Bennett Michael, James E. Bennett, James E. Bennett, Michael J. Flynn, Michael J. Flynn, Michael J. Flynn , 1995
"... This paper introduces three performance factors for dynamically scheduled superscalar processors. These factors, availability, efficiency, and utility, are then used to explain the variations in performance that occur with different processor and memory system features. The processor features that a ..."
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This paper introduces three performance factors for dynamically scheduled superscalar processors. These factors, availability, efficiency, and utility, are then used to explain the variations in performance that occur with different processor and memory system features. The processor features

Sentinel scheduling for VLIW and superscalar processors

by Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu - In asplos5 , 1992
"... Speculative execution is an important source of parallelism for VLIW and superscalar processors. A serious challenge with compiler-controlled speculative execution is to accurately detect and report all program execution errors at the time of occurrence. In this paper, a set of architectural feature ..."
Abstract - Cited by 61 (10 self) - Add to MetaCart
Speculative execution is an important source of parallelism for VLIW and superscalar processors. A serious challenge with compiler-controlled speculative execution is to accurately detect and report all program execution errors at the time of occurrence. In this paper, a set of architectural
Results 1 - 10 of 1,225