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Clock Skew Tolerant Communication Scheme for SoC IP Blocks
"... Abstract — System-on-chip (SoC) designs have different intellectual property (IP) blocks that operate on independent clocks and signals crossing the clock domains could experience errors. This paper details the effects of clock skew on data and clock signals at the interface logic of communicating S ..."
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Abstract — System-on-chip (SoC) designs have different intellectual property (IP) blocks that operate on independent clocks and signals crossing the clock domains could experience errors. This paper details the effects of clock skew on data and clock signals at the interface logic of communicating
Coding for Skew-Tolerant Parallel Asynchronous Communications
- IEEE Transactions on Information Theory
, 1993
"... Abstract- Consider a communication channel that consists of several subchannels transmitting simultaneously and asyn-chronously. As an example of this scheme, consider a board with several chips. The subchannels represent wires connecting between the chips where differences in the lengths of the wir ..."
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Cited by 4 (0 self)
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and sufficient conditions for codes that can detect skew as well as for codes that are skew-tolerant, i.e., they can correct the skew and allow continuous operation, are derived. Codes have been constructed that satisfy the necessary and sufficient conditions, their opti-mality studied, and efficient decoding
Efficient Verification of Timed Automata using Dense and Discrete Time Semantics
"... In this paper we argue that the semantic issues of discrete vs. dense time should be separated as much as possible from the pragmatics of state-space representation. Contrary to some misconceptions, the discrete semantics is not inherently bound to use state-explosive techniques any more than the de ..."
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Cited by 27 (5 self)
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more efficiently by taking into account the activity of clocks, to eliminate redundancy. To support these claims we report experimental results obtained using an extension of Kronos with BDDs and variable-dimension DBMs where we veri ed the asynchronous chip STARI, a FIFO bu er which provides for skew-tolerant
2Information and Communications
"... Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with minimum skew and latency. While there are a few related works in literature, none of them considers the reliability of T ..."
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Cited by 2 (0 self)
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Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with minimum skew and latency. While there are a few related works in literature, none of them considers the reliability
Application-bypass reduction for large-scale clusters
- in Proceedings of IEEE International Symposium on Cluster Computing (Cluster 2003), (Hongkong
, 2003
"... Abstract — Process skew is an important factor in the performance of parallel applications, especially in large-scale clusters. Reduction is a common collective operation which, by its nature, introduces implicit synchronization between the processes involved in the communication and is therefore hi ..."
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Cited by 8 (3 self)
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implementation. In addition, we see that this factor of improvement increases with system size, indicating that the application-bypass implementation is more scalable and skew-tolerant than the default non-application-bypass version. This framework promises design and development of highperformance and scalable
A Minimal Source-Synchronous Interface
- IN PROCEEDINGS OF THE 15TH IEEE ASIC/SOC CONFERENCE
, 2002
"... We present a novel implementation of source synchronous communication. Our design appears to the designer as a latch with two clock inputs, one from the transmitter and the other from the receiver. Our circuit is simple and provides a skew tolerance of nearly two clock periods. The analog dynamics o ..."
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Cited by 20 (2 self)
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We present a novel implementation of source synchronous communication. Our design appears to the designer as a latch with two clock inputs, one from the transmitter and the other from the receiver. Our circuit is simple and provides a skew tolerance of nearly two clock periods. The analog dynamics
A New Technique for Removing Jitter in Network Multimedia Communication to Achieve Guaranteed QoS over Packet Network
"... Multimedia data are sensed by human. These types of data are delay intolerable but error tolerable to some extend. Two important parameters that degrade the quality of service (QoS) of multimedia services are Skew and Jitter. Achieving guaranteed Quality of Service (QoS) of multimedia service is a g ..."
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Multimedia data are sensed by human. These types of data are delay intolerable but error tolerable to some extend. Two important parameters that degrade the quality of service (QoS) of multimedia services are Skew and Jitter. Achieving guaranteed Quality of Service (QoS) of multimedia service is a
Surviving failures in bandwidthconstrained datacenters
- In Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication, SIGCOMM ’12
, 2012
"... Abstract-Datacenter networks have been designed to tolerate failures of network equipment and provide sufficient bandwidth. In practice, however, failures and maintenance of networking and power equipment often make tens to thousands of servers unavailable, and network congestion can increase servi ..."
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Cited by 12 (1 self)
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usage, but also decreases fault tolerance. We present a detailed analysis of a large-scale Web application and its communication patterns. Based on that, we propose and evaluate a novel optimization framework that achieves both high fault tolerance and significantly reduces bandwidth usage
RR81] Richard F. Rashid and George G. Robertson. Accent: A communication oriented
- Ph.D. thesis, The Norwegian Institute of Technology
, 1995
"... orting fault-tolerance in a parallel database server. International Journal of Computer Systems Science & Engineering, 9(2):134--141, April 1994. [WB87] W. Kevin Wilkinson and Haran Boral. KEV --- A kernel for Bubba. In Masaru Kitsuregawa and Hidehiko Tanaka, editors, Database Machines and Know ..."
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orting fault-tolerance in a parallel database server. International Journal of Computer Systems Science & Engineering, 9(2):134--141, April 1994. [WB87] W. Kevin Wilkinson and Haran Boral. KEV --- A kernel for Bubba. In Masaru Kitsuregawa and Hidehiko Tanaka, editors, Database Machines
A Minimal Source-Synchronous Interface data PLL
"... We present a novel implementation of source synchronous communication. Our design appears to the designer as a latch with two clock inputs, one from the transmitter and the other from the receiver. Our circuit is simple and provides a skew tolerance of nearly two clock periods. The analog dynamics o ..."
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We present a novel implementation of source synchronous communication. Our design appears to the designer as a latch with two clock inputs, one from the transmitter and the other from the receiver. Our circuit is simple and provides a skew tolerance of nearly two clock periods. The analog dynamics
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