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Secure AES Hardware Module for Resource Constrained Devices

by Elena Trichina, Tymur Korkishko
"... Abstract. Low power consumption, low gate count, and high throughput are standard design criteria for cryptographic coprocessors designated for resource constrained devices such as smart cards. With the advent of side channel attacks, devices ’ resistance to such attacks became another major require ..."
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, this is the first implementation of a side channel-resistant AES hardware module suitable for smart- and SIM-cards. 1

A Side-Channel Analysis Resistant Description of the AES S-box

by Elisabeth Oswald, Stefan Mangard, Norbert Pramstaller - In Fast Software Encryption, 12th International Workshop, FSE 2005
"... Abstract. So far, efficient algorithmic countermeasures to secure the AES algorithm against (first-order) differential side-channel attacks have been very expensive to implement. In this article, we introduce a new masking countermeasure which is not only secure against first-order sidechannel attac ..."
Abstract - Cited by 62 (2 self) - Add to MetaCart
Abstract. So far, efficient algorithmic countermeasures to secure the AES algorithm against (first-order) differential side-channel attacks have been very expensive to implement. In this article, we introduce a new masking countermeasure which is not only secure against first-order sidechannel

Rijmen: A Side-Channel Analysis Resistant Description of the AES S-box

by Elisabeth Oswald, Stefan Mangard, Norbert Pramstaller - Fast Software Encryption 2005, LNCS 3557 , 2005
"... Abstract. So far, efficient algorithmic countermeasures to secure the AES algorithm against (first-order) differential side-channel attacks have been very expensive to implement. In this article, we introduce a new masking countermeasure which is not only secure against first-order side-channel atta ..."
Abstract - Cited by 4 (0 self) - Add to MetaCart
Abstract. So far, efficient algorithmic countermeasures to secure the AES algorithm against (first-order) differential side-channel attacks have been very expensive to implement. In this article, we introduce a new masking countermeasure which is not only secure against first-order side-channel

Private Circuits: Securing Hardware against Probing Attacks

by Yuval Ishai, Amit Sahai, David Wagner - In Proceedings of CRYPTO 2003 , 2003
"... Abstract. Can you guarantee secrecy even if an adversary can eavesdrop on your brain? We consider the problem of protecting privacy in circuits, when faced with an adversary that can access a bounded number of wires in the circuit. This question is motivated by side channel attacks, which allow an a ..."
Abstract - Cited by 128 (7 self) - Add to MetaCart
an adversary to gain partial access to the inner workings of hardware. Recent work has shown that side channel attacks pose a serious threat to cryptosystems implemented in embedded devices. In this paper, we develop theoretical foundations for security against side channels. In particular, we propose several

Successfully Attacking Masked AES Hardware Implementations

by Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald - Cryptographic Hardware and Embedded Systems – CHES 2005, 7th International Workshop
"... Abstract. During the last years, several masking schemes for AES have been proposed to secure hardware implementations against DPA attacks. In order to investigate the effectiveness of these countermeasures in practice, we have designed and manufactured an ASIC. The chip features an unmasked and two ..."
Abstract - Cited by 57 (3 self) - Add to MetaCart
leak side-channel information due to glitches at the output of logic gates. It turns out that masking the AES S-Boxes does not prevent DPA attacks, if glitches occur in the circuit.

Towards sound approaches to counteract power-analysis attacks

by Suresh Chari, Charanjit S. Jutla, Josyula R. Rao, Pankaj Rohatgi , 1999
"... Abstract. Side channel cryptanalysis techniques, such as the analysis of instantaneous power consumption, have been extremely e ective in attacking implementations on simple hardware platforms. There are several proposed solutions to resist these attacks, most of which are ad{hoc and can easily be r ..."
Abstract - Cited by 159 (0 self) - Add to MetaCart
Abstract. Side channel cryptanalysis techniques, such as the analysis of instantaneous power consumption, have been extremely e ective in attacking implementations on simple hardware platforms. There are several proposed solutions to resist these attacks, most of which are ad{hoc and can easily

Using Secure Coprocessors

by Bennet Yee , 1994
"... The views and conclusions in this document are those of the authors and do not necessarily represent the official policies or endorsements of any of the research sponsors. How do we build distributed systems that are secure? Cryptographic techniques can be used to secure the communications between p ..."
Abstract - Cited by 165 (8 self) - Add to MetaCart
assumption upon which secure distributed systems are built; without this foundation even the best cryptosystem or the most secure kernel will crumble. In this thesis, I address the distributed security problem by proposing the addition of a small, physically secure hardware module, a secure coprocessor

FIDES: Lightweight authenticated cipher with side-channel resistance for constrained hardware

by Andrey Bogdanov, Florian Mendel, Qingju Wang - In CHES 2013, LNCS
"... Abstract. In this paper, we present a novel lightweight authenticated cipher optimized for hardware implementations called Fides. It is an online nonce-based authenticated encryption scheme with authenticated data whose area requirements are as low as 793 GE and 1001 GE for 80-bit and 96-bit securit ..."
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, cryptographically optimal 5-bit and 6-bit S-boxes are used as basic nonlinear components while paying a special attention on the simplicity of providing first order side-channel resistance with threshold implementation.

K.: Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations

by Stefan Mangard, Kai Schramm - In: CHES. LNCS
"... Abstract. This article starts with a discussion of three different attacks on masked AES hardware implementations. This discussion leads to the conclusion that glitches in masked circuits pose the biggest threat to masked hardware implementations in practice. Motivated by this fact, we pinpointed wh ..."
Abstract - Cited by 16 (0 self) - Add to MetaCart
which parts of masked AES S-boxes cause the glitches that lead to side-channel leakage. The analysis reveals that these glitches are caused by the switching characteristics of XOR gates in masked multipliers. Masked multipliers are basic building blocks of most recent proposals for masked AES S

An Information-Theoretic Model for Adaptive Side-Channel Attacks

by Boris Köpf, David Basin - CCS'07 , 2007
"... We present a model of adaptive side-channel attacks which we combine with information-theoretic metrics to quantify the information revealed to an attacker. This allows us to express an attacker’s remaining uncertainty about a secret as a function of the number of side-channel measurements made. We ..."
Abstract - Cited by 85 (8 self) - Add to MetaCart
We present a model of adaptive side-channel attacks which we combine with information-theoretic metrics to quantify the information revealed to an attacker. This allows us to express an attacker’s remaining uncertainty about a secret as a function of the number of side-channel measurements made. We
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