IPC over standard LRU. Our results show that smart cache management and scheduling is essential to achieve high performance with shared cache memory.

The Setting: Computer science and engineering is undergoing a revolution. Computationally very powerful parallel computers, which used to be the luxury of the government and billion-dollar corporations, are already in the laptops and desktops of millions of ordinary users. Computer architects are building existing computer chips with multiple processing cores inside them, as opposed to with solely a single processing core, which used to be the traditional way of designing mainstream computer chips until around 2004. Essentially, a processing core is analogous to the brain of the computing system: the more cores there are, the more tasks the system can perform in parallel. Chips with multiple processing cores are commonly called multi-core chips. Existing Intel and AMD chips in the market already have 4 cores, IBM and Sun Microsystems have chips with respectively 9 and 16 cores, and Intel has demonstrated prototypes of an 80-core chip. Both academic and industrial researchers, including us at Carnegie Mellon, are envisioning and charting out designs of 1000core chips in the 10-20-year timeframe [1, 2]. Soon, unprecedented amounts of computing power will be in the hands of almost every single computer user and programmer. And, both the programmers and the users need to be aware of how to harness this power. To aid understanding, Figure 1 shows an example single-core system and an example multi-core system with nine processing cores. Major differences between the two systems are highlighted in terms of designers’, programmers ’ and users ’ perspectives. Multi−Core Chip

This paper investigates the problem of partitioning a shared cache between multiple concurrently executing applications. The commonly used LRU policy implicitly partitions a shared cache on a demand basis, giving more cache resources to the application that has a high demand and fewer cache

We present a low-overhead method for accurately measuring application performance (CPI) and off-chip bandwidth (GB/s) as a function of its the available shared cache capacity, on real hardware, with no modifications to the application or operating system. We accomplish this by co-running a Pirate

The sharing of caches among Web proxies is an important technique to reduce Web traffic and alleviate network bottlenecks. Nevertheless it is not widely deployed due to the overhead of existing protocols. In this paper we propose a new protocol called "Summary Cache"; each proxy keeps a

the performance impact of a multithreaded architecture on the storage hierarchy. Particularly, we examined the effects of different multithread scheduling techniques on cache performance. Using several program traces representing typical server/workstation workload mix, we found that the cache performance can

Paging for multi-core processors extends the classical paging problem to a setting in which several processes simultaneously share the cache. Recently, Hassidim proposed a model for multi-core paging [25], studying cache eviction policies for multi-cores under the traditional competitive analysis

Abstract—On multicore processors, applications are run shar-ing the cache. This paper presents online optimization to co-locate applications to minimize cache interference to maximize performance. The paper formulates the optimization problem and solution, presents a new sampling technique

the performance of a cluster-based multiprocessor architecture in which processors within a cluster are tightly coupled via a shared cluster cache for various processor-cache configurations. Our results show that for parallel applications, clustering via shared caches provides an effective mechanism

Abstract---In data intensive applications of Cloud Computing such as XML parsing, large graph traversing and so on, there are a lot of operations to access irregular data. These data need be timely prefetched into the shared cache in CMPs by helper thread. However, a bad prefetching strategy