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100
Optical Multiplexer Board for TileCal Data Redundancy.
"... This work describes the present status and future evolution of the Optical Multiplexer Board (OMB) for the ATLAS Tile Calorimeter. The developments currently under execution include the adaptation and test of this card to TileCal needs and the design and implementation of the CRC (Cyclic Redundancy ..."
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This work describes the present status and future evolution of the Optical Multiplexer Board (OMB) for the ATLAS Tile Calorimeter. The developments currently under execution include the adaptation and test of this card to TileCal needs and the design and implementation of the CRC (Cyclic Redundancy
Classification of tilings of the 2-dimensional sphere by congruent triangles
- Hiroshima Math. J
, 2002
"... We give a new classification of tilings of the 2-dimensional sphere by congruent triangles accompanied with a complete proof. This accomplishes the old classification by Davies, who only gave an outline of the proof, regrettably with some redundant tilings. We clarify Davies ’ obscure points, give a ..."
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Cited by 16 (0 self)
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We give a new classification of tilings of the 2-dimensional sphere by congruent triangles accompanied with a complete proof. This accomplishes the old classification by Davies, who only gave an outline of the proof, regrettably with some redundant tilings. We clarify Davies ’ obscure points, give
Efficient tiling for an ODE discrete integration program: redundant tasks
"... In this paper, we present an efficient and simple solution to the parallelization of discrete integration programs of ordinary differential equations (ODE). The main technique used is known as loop tiling. To avoid the overhead due to code complexity and border effects, we introduce redundant tasks ..."
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Cited by 1 (0 self)
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In this paper, we present an efficient and simple solution to the parallelization of discrete integration programs of ordinary differential equations (ODE). The main technique used is known as loop tiling. To avoid the overhead due to code complexity and border effects, we introduce redundant tasks
Hierarchical Overlapped Tiling
"... This paper introduces hierarchical overlapped tiling, a transformation that applies loop tiling and fusion to conventional loops. Overlapped tiling is a useful transformation to reduce communication overhead, but it may also generate a significant amount of redundant computation. Hierarchical overla ..."
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Cited by 13 (1 self)
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This paper introduces hierarchical overlapped tiling, a transformation that applies loop tiling and fusion to conventional loops. Overlapped tiling is a useful transformation to reduce communication overhead, but it may also generate a significant amount of redundant computation. Hierarchical
Self-healing tile sets
- Foundations of Nanoscience: Self-Assembled Architectures and Devices, 2005
, 2005
"... Summary. Molecular self-assembly appears to be a promising route to bottom-up fabrication of complex objects. Two major obstacles are how to create structures with more interesting organization than periodic or finite arrays, and how to reduce the fraction of side products and erroneous assemblies. ..."
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Cited by 15 (1 self)
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. Algorithmic self-assembly provides a theoretical model for investigating these questions: the growth of arbitrarily complex objects can be programmed into a set of Wang tiles, and their robustness to a variety of possible errors can be studied. The ability to program the tiles presents an alternative
TILING OPTIMIZATIONS FOR STENCIL COMPUTATIONS
, 2013
"... This thesis studies the techniques of tiling optimizations for stencil programs. Traditionally, research on tiling optimizations mainly focuses on tessellating tiling, atomic tiles and regular tile shapes. This thesis studies several novel tiling techniques which are out of the scope of traditional ..."
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Cited by 2 (0 self)
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overhead by introducing redundant computations. Hierarchical Overlapped Tiling also applies the idea of hierarchical tiling to take advantage of hardware hierarchy, so that the additional overhead introduced by redundant computations can be minimized. The second tiling technique is called Conjugate
Compact Error-Resilient Computational DNA Tiling Assemblies
"... The self-assembly process for bottom-up construction of nanostructures is of key importance to the emerging of the new scientific discipline of Nanoscience. For example, the self-assembly of DNA tile nanostructures into 2D and 3D lattices can be used to perform parallel universal computation and to ..."
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Cited by 53 (10 self)
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an error-resilient tiling using 2-way overlay redundancy such that a single pad mismatch between a tile and its immediate neighbor forces at least one further pad mismatch between a pair of adjacent tiles in the neighborhood of this tile. This drops the error rate from # to appr...
Defect tolerance of QCA tiles
- in Proc. 2006 Design, Automation and Test in Europe (DATE ’06
"... Quantum dot Cellular Automata (QCA) is one of the promising technologies for nano scale implementation. The operation of QCA systems is based on a new paradigm gen-erally referred to as processing-by-wire (PBW). This paper analyzes the defect tolerance properties of PBW when tiles are employed using ..."
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Cited by 1 (0 self)
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that novel features of PBW are possi-ble due to spatial redundancy and QCA tiles are robust and inherently defect tolerant. Index words: QCA, defect tolerance, emerging technolo-gies. 1.
Optimized Visualization for Tiled Displays
"... In this paper we present new functionality we added to the Chromium framework. When driving tiled displays using a sort-first configuration based on the Tilesort stream procession unit (SPU) the performance bottlenecks are the high utilization of the client host caused by the expensive sorting and b ..."
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Cited by 2 (0 self)
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In this paper we present new functionality we added to the Chromium framework. When driving tiled displays using a sort-first configuration based on the Tilesort stream procession unit (SPU) the performance bottlenecks are the high utilization of the client host caused by the expensive sorting
Enhanced Reliability in Tiled Manycore Architectures through Transparent Task Relocation
"... Abstract: Manycore platforms with tens and even up to hundreds of processing cores per chip are becoming a commercial reality and are subject of intensified research. This concept paper describes work in progress on the applicability of HW supported communication and processing virtualization on reg ..."
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on regular structured, tiled manycore ar-chitectures for the benefit of improved fault tolerance against transient and permanent perturbations. Temporarily unused, naturally redundant tiles are dynamically occu-pied during run time via transparent task relocation. This means, the execution of a task can pro
Results 1 - 10
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100
