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A Survey of Reconfigurable Architectures
"... A new architecture type that is recently evolving is the reconfigurable architecture which combines the benefits of ASIPs (Application Specific Instruction Set Processors) and FPGAs (Field Programmable Gate Arrays). Reconfigurable computing combines software flexibility with high performance hardwar ..."
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A new architecture type that is recently evolving is the reconfigurable architecture which combines the benefits of ASIPs (Application Specific Instruction Set Processors) and FPGAs (Field Programmable Gate Arrays). Reconfigurable computing combines software flexibility with high performance
Data Partitioning for Reconfigurable Architectures with
- Distributed Block RAM” – International Workshop on Logic and Synthesis (IWLS
, 2005
"... Contemporary reconfigurable architectures integrate distributed block RAM modules on-chip to provide ample storage for DSP, wireless, and image processing applications. Synthesizing applications to these complex systems requires an effective and efficient approach to conduct data partitioning and st ..."
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Cited by 1 (0 self)
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Contemporary reconfigurable architectures integrate distributed block RAM modules on-chip to provide ample storage for DSP, wireless, and image processing applications. Synthesizing applications to these complex systems requires an effective and efficient approach to conduct data partitioning
Loop Parallelization for Reconfigurable Architectures
"... Abstract—Reconfigurable Computing (RC) is one of the research directions that focuses on accelerating applications. In the presented approach we assume the Molen machine organization and the Molen programming paradigm as our framework. Molen combines a general purpose processor (GPP) and a Field Pro ..."
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Cited by 1 (1 self)
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Programmable Gate Array (FPGA), having the advantages of both speed of hardware and flexibility of software execution. In this paper we present a method that allows complete automation of efficient code generation with the Molen compiler for reconfigurable architectures in Delft WorkBench project. The proposed
Smart Memories: A Modular Reconfigurable Architecture
, 2000
"... Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these conflicting requirements, we propose a modular rec ..."
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Cited by 190 (9 self)
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reconfigurable architecture called Smart Memories, targeted at computing needs in the 0.1μm technology generation. A Smart Memories chip is made up of many processing tiles, each containing local memory, local interconnect, and a processor core. For efficient computation under a wide class of possible
Shared Reconfigurable Architectures for CMPs
- In Proc. 18th IEEE Int’l Conference on Field Programmable Logic and Applications
, 2008
"... This paper investigates reconfigurable architectures suit-able for chip multiprocessors (CMPs). Prior research has established that augmenting a conventional processor with reconfigurable logic can dramatically improve the perfor-mance of certain application classes, but this comes at non-trivial po ..."
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Cited by 3 (2 self)
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This paper investigates reconfigurable architectures suit-able for chip multiprocessors (CMPs). Prior research has established that augmenting a conventional processor with reconfigurable logic can dramatically improve the perfor-mance of certain application classes, but this comes at non
With Dynamic Reconfiguration Architecture ABSTRACT
"... Reconfigurable computing has been proposed for image and signal processing applications with various objectives, including high performance, flexibility, specialization, and most recently, adaptability. Reconfiguration is characterized by how fast the reconfiguration can occur and how many possible ..."
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hardware resources are dynamically allocated to meet the MDPP requirements of the application. These architectures can be characterized via a set of architectural parameters which can be determined experimentally. In this work, the analysis and hardware implementation of a dynamic reconfigurable unit based
Mapping Loops onto Reconfigurable Architectures
- 8TH INTERNATIONAL WORKSHOP ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS
, 1998
"... Reconfigurable circuits and systems have evolved from application specific accelerators to a general purpose computing paradigm. But the algorithmic techniques and software tools are also heavily based on the hardware paradigm from which they have evolved. Loop statements in traditional programs con ..."
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Cited by 15 (10 self)
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consist of regular, repetitive computations which are the most likely candidates for performance enhancement using configurable hardware. This paper develops a formal methodology for mapping loops onto reconfigurable architectures. We develop a parameterized abstract model of reconfigurable architectures
Dynamically Reconfigurable Architectures
"... Abstract: Partial dynamic reconfiguration of FPGAs was investigated for video-based driver assistance applications during the last 4 years. High-level application software was combined with dynamically reconfigurable hardware accelerators in selected scenarios, e.g. vehicle lights detection, optical ..."
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Abstract: Partial dynamic reconfiguration of FPGAs was investigated for video-based driver assistance applications during the last 4 years. High-level application software was combined with dynamically reconfigurable hardware accelerators in selected scenarios, e.g. vehicle lights detection
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