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Table 5 : Times required for filter reconfiguration and writing partial bitstreams for filter

in An FPGA-Based Run-Time Reconfigurable 2-D Discrete Wavelet Transform Core
by Jonathan B. Ballagh 2001
"... In PAGE 10: ........... 71 Table5 : Times required for filter reconfiguration and writing partial bitstreams for filter banks of varying number of taps. The partial bitstream file size is also reported for each configuration.... ..."
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Table 5: Times required for filter reconfiguration and writing partial bitstreams for filter

in An FPGA-Based Run-Time Reconfigurable 2-D Discrete Wavelet Transform Core
by Jonathan B. Ballagh 2001
Cited by 3

Table 1: Local reconfiguration table

in Reconfigurable Parallel Computer Architecture Based on Wavelength-Division Multiplexed Optical Interconnection Network
by Khaled Aly, Patrick W. Dowd
"... In PAGE 7: ... Recon gurationTwo steps are needed to accomplish reconfiguration: processor set re-labeling and filters re-tuning. The information relevant to each embedding are stored in a local table ( Table1 ) at each processor and retrieved in response to a reconfiguration command. 5.... ..."

Table 1. An example reconfigurable architecture Category Parameter Value

in Mapping Loops on Coarse-Grain Reconfigurable Architectures Using Memory Operation Sharing
by Jong-eun Lee, Kiyoung Choi, Nikil Dutt 2002
"... In PAGE 9: ...ew variables such as parameters or computation results (e.g., scalar product). The DRAA can be defined at three levels: PE microarchitecture, line architecture, and reconfigurable plane architec- ture. Table1 lists the parameters for an example DRAA architecture. 3.... In PAGE 21: ...mem. op. #repetition hydro Hydrodynamic excerpt from LL 4 40 ICCG Incomplete Cholesky-conjugate gradient from LL 6 40 banded Banded linear equations (unrolled) from LL 14 3 state equations of state from LL 10 12 ADI Alternating direction, implicit integration (innermost, part) from LL 11 7 diff First difference from LL 3 98 wavelet A wavelet filter implementation (innermost) 5 24 ME Motion estimation kernel (unrolled) from MPEG encoder 128 30 AF The set of join nodes in Pi is a subset of the set of join nodes in PiB71.16 6 Experiments For our experiments, we used the example architecture described in Table1 . For the line inter- connections, nearest neighbor connections and global buses are used, where global buses may also be used as memory buses.... ..."
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Table 1: Kinds of Reconfigurations.

in Reconfiguration in the Enterprise JavaBean component model
by Matthew J. Rutherford, Kenneth Anderson, Antonio Carzaniga, Antonio Carzaniga, Dennis Heimbigner, Dennis Heimbigner, Er L. Wolf, Er L. Wolf 2002
"... In PAGE 3: ... Further framing the problem, we delineated a space of reconfigurations that we wished to address in the study. This space is shown in Table1 . We consider three media of modifications leading to reconfiguration: parameters, implementations, and interfaces.... In PAGE 11: ... Table 2 summarizes a sequence of reconfigurations that we applied to a simple scenario of Dirsync running on two nodes, N-1 and N-2. Those particular reconfigurations were chosen because they represent a range of modifications commonly applied to component-based distributed systems and because they cover the space of reconfigurations outlined in Table1 of Section 1. We collected some initial performance statistics that indicate reasonable overhead in carrying out the reconfigurations.... ..."
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Table 1 Reconfiguration overhead

in DR-TCP: Downloadable and reconfigurable TCP
by Jae-hyun Hwang A, Jin-hee Choi B, Se-won Kim A, Chuck Yoo A 2007
"... In PAGE 13: ... To clock delayed time due to process reconfiguration precisely, we use Time Stamp Counter (TSC) timer, which is a high resolution timer supported by Intel Pentium processor (Kris Kaspersky, 2003). Table1 shows the reconfiguration overhead without upgrade process. We divide the reconfiguration process into two steps, which are: (1) creating SM objects and (2) searching transition tables since the first step is not required if the objects Please cite this article in press as: Hwang, J.... ..."

Table 1. Reconfiguration Performance

in A Versatile Framework for FPGA Field Updates: An Application of Partial Self- Reconfiguration
by unknown authors
"... In PAGE 5: ... The user application area allocation was varied to obtain reconfiguration times for different area sizes. These results are shown in Table1 . The data transferred, which included header and CRC overheads, was proportional to the area.... ..."

Table 4. Reconfiguration time

in SELF-RECONFIGURABLE PERVASIVE PLATFORM FOR CRYPTOGRAPHIC APPLICATION
by Arnaud Lagger, Andres Upegui
"... In PAGE 5: ... The more convenient way to do this is to open a persistent FTP connection and then retrieve the bitstreams successively. Table4 shows, for each partial bitstream, the reconfiguration time for each scenario. Table 4.... ..."

Table 1. Reconfiguration time

in Architecture of a Reconfigurable Processor for Implementing Search Algorithms over Discrete Matrices
by Valery Sklyarov, Iouliia Skliarova 2003
"... In PAGE 9: ... The results [35] have shown that the utilized universal circuits of reprogrammable FSMs require similar hardware resources and their timing characteristics are comparable with uniquely designed FSM circuits that cannot be reused. Table1 presents the time required for dynamic loading of memory blocks with different parameters through the second port. Table 1.... In PAGE 9: ...The working frequency for the FPGA XCV812E to be used for experiments was set to 30 MHz. The first line of Table1 contains the required time for reloading the segment register, which activates the required group of RAM segments [35,36]. The other lines show the loading time for RAM blocks.... ..."
Cited by 4

Table 1. Reconfiguration time.

in A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors
by Valery Sklyarov, Iouliia Skliarova, Arnaldo Oliveira, António B. Ferrari 2003
"... In PAGE 7: .... Parallel port of PC for the XC4010XL FPGA. For such purposes we have used the XS40 and XStend boards of XESS linked to the PC parallel port (this implementation was considered just for educational purposes). Table1 shows the time required for dynamic loading of memory blocks with different parameters through the PCI. The working frequency for the used XCV812E FPGA was set to 30 MHz.... ..."
Cited by 3
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