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Table 1: Hardware-Supported vs. Software-Only Implementations 8-processor shared memory multiprocessor con guration consisting of two multiprocessor modules each containing four Motorola (25 Mhz) 68040 processors sharing an L2 cache that supports our optimizations. As in Fig. 4, multiple multiprocessor boards share an L3 cache, where the consistency is controlled by kernel software. Although this hardware that we designed and implemented is not the fastest available at this time, we argue that the logical design is applicable to much faster processors, and a faster processor would not signi cantly reduce the bene ts of our optimizations (see Section 6).

in Optimized Memory-Based Messaging: Leveraging the Memory System for High-Performance Communication
by David Cheriton, Robert A. Kutter 1996
"... In PAGE 15: ... In this implementation, the sender traps to the kernel, and uses a queue and inter-processor interrupt to notify the receiver of the signal. Table1 compares this software-only version with our optimized messaging implementation, listing the execution times (and MC68040 instruction counts) of various kernel and user-level com- ponents for these two implementations. These measurements show that using all three hardware optimizations provide a factor of two reduction in kernel overhead even in a small-scale system.... ..."
Cited by 5

Table 5.1: RAM for 8 Chunk Processors Shared Not Shared

in An Fpga Implementation Of Atr Using Embedded Ram For Control
by Richard D. Ross

Table 5.1: RAM for 8 Chunk Processors Shared Not Shared

in EMBEDDED RAM FOR CONTROL
by Richard D. Ross

Table 5: Execution times in seconds for quicksort of 500,000 items using a shared queue on a single processor (no contention).

in Non-blocking Algorithms and Preemption-Safe Locking on Multiprogrammed Shared Memory Multiprocessors
by Maged M. Michael, Michael L. Scott 1998
"... In PAGE 23: ... In each execution, the processes cooperate in sorting an array of 500,000 pseudo-random numbers using quicksort for intervals of more than 20 elements, and insertion sort for smaller intervals. Figure 10 and Table5 show performance results for the three queue-based versions; figure 11 and Table 6 show results for the three stack-based versions. Execution times are normalized to those of the preemption-safe lock-based algorithms.... ..."
Cited by 50

Table 5: Execution times in seconds for quicksort of 500,000 items using a shared queue on a single processor (no contention).

in Non-Blocking Algorithms and Preemption-Safe Locking on Multiprogrammed Shared Memory Multiprocessors
by Maged M. Michael, Michael L. Scott 1998
"... In PAGE 23: ... In each execution, the processes cooperate in sorting an array of 500,000 pseudo-random numbers using quicksort for intervals of more than 20 elements, and insertion sort for smaller intervals. Figure 10 and Table5 show performance results for the three queue-based versions; figure 11 and Table 6 show results for the three stack-based versions. Execution times are normalized to those of the preemption-safe lock-based algorithms.... ..."
Cited by 50

Table 4.5: Computation time (in seconds) for K6 - K8 with p processors (Shared Memory)

in Parallel Computation and Graphical Visualization of the Minimum Crossing Number of a Graph
by Umid Tadjiev

Table 4.6: E ciency for K8 as a function of p processors (Shared Memory)

in Parallel Computation and Graphical Visualization of the Minimum Crossing Number of a Graph
by Umid Tadjiev

Table 4.5: Computation time (in seconds) for K6 - K8 with p processors (Shared Memory)

in Parallel Computation and Graphical Visualization of the Minimum Crossing Number of a Graph
by Umid Tadjiev, To My Gr, Khasan Rasulev

Table 4.6: E ciency for K8 as a function of p processors (Shared Memory)

in Parallel Computation and Graphical Visualization of the Minimum Crossing Number of a Graph
by Umid Tadjiev, To My Gr, Khasan Rasulev

Table 4 shows some of the experimental results. The third row in this table gives time taken to reach the solution and last two rows give number of processors and shared memo- ries synthesized for some of the problem instances. When- ever, more than one shared memory modules were instan- tiated, we obtained the interconnection network similar to the architecture of Figure 13. We did these experiments on a workstation with Intel XEON [17] CPU running at 2.20GHz. It can be observed that the solutions for all these process networks took less than one second. It can be no- ticed that RPNG allowed one to conduct a large number of application speci c multiprocessor synthesis experiments by quickly producing a number of test cases.

in RPNG: A Tool for Random Process Network Generation Basant Kumar Dwivedi Calypto Design Systems (I) Pvt. Ltd.
by Th Floor, Som Datt Tower
"... In PAGE 9: ... Target architecture template Number of processes 10 20 30 Number of queues 19 57 60 Time taken in Sol. lt;1 sec lt;1 sec lt;1 sec Number of instantiated processors 3 5 9 Number of shared memories 1 8 8 Table4 . Experiments using RPNG 8 Conclusions We presented a tool for randomly generating process networks which can be used for generating test cases for synthesis of application speci c multiprocessor architec- tures.... ..."
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