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2,862
Functional and Timing Validation of Partially Bypassed Processor Pipelines
"... Customizing the bypasses in pipelined processors is an effective and popular means to perform power, performance and complexity trade-offs in embedded systems. However existing techniques are unable to automatically generate test patterns to functionally validate a partially bypassed processor. Manu ..."
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Cited by 1 (0 self)
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Customizing the bypasses in pipelined processors is an effective and popular means to perform power, performance and complexity trade-offs in embedded systems. However existing techniques are unable to automatically generate test patterns to functionally validate a partially bypassed processor
Processor Pipelines and Static Worst-Case Execution Time Analysis
, 2002
"... Engblom, J. 2002: Processor Pipelines and Static Worst-Case Execution Time Analysis. Acta Universitatis Upsaliensis. Uppsala dissertations from the Faculty of Science and Technology 36. 130 pp. Uppsala. ISBN 91-554-5228-0. ..."
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Cited by 68 (11 self)
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Engblom, J. 2002: Processor Pipelines and Static Worst-Case Execution Time Analysis. Acta Universitatis Upsaliensis. Uppsala dissertations from the Faculty of Science and Technology 36. 130 pp. Uppsala. ISBN 91-554-5228-0.
The Performance Impact of Incomplete Bypassing in Processor Pipelines
- In Proceedings of the 28th Annual International Symposium on Microarchitecture
, 1995
"... Pipelined processors employ hardware bypassing to eliminate certain pipeline hazards. Bypassing is logically simple but can be costly, especially in wide issue and deeply pipelined machines. In this paper bypassing is studied in detail, with an emphasis on designs in which the bypassing network is n ..."
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Cited by 36 (0 self)
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Pipelined processors employ hardware bypassing to eliminate certain pipeline hazards. Bypassing is logically simple but can be costly, especially in wide issue and deeply pipelined machines. In this paper bypassing is studied in detail, with an emphasis on designs in which the bypassing network
Processor Pipelines and Their Properties for Static WCET Analysis
- Proceedings of EMSOFT 02: Second International Conference on Embedded Software, volume 2491 of Lecture Notes in Computer Science
, 2002
"... When developing real-time systems, the worst-case execution time (WCET) is a commonly used measure for predicting and analyzing program and system timing behavior. Such estimates should preferrably be provided by static WCET analysis tools. Their analysis is made difficult by features of common ..."
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
, 2004
"... The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and protecting against single-event upsets in digital systems. In this work, the effects of transient faults on high performance microprocessors is explored. To perform a tho ..."
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Cited by 132 (4 self)
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thorough exploration, a highly detailed register transfer level model of a deeply pipelined, out-of-order microprocessor was created. Using fault injection, we determined that fewer than 15% of single bit corruptions in processor state result in software visible errors. These failures were analyzed
Processor Pipeline Design for Fast Network Message Handling in RWC-1 Multiprocessor
, 1998
"... this paper we describe the pipeline design and enhanced hardware for fast message handling in a RICA-1 processor, a processing element (PE) in the RWC-1 multiprocessor. The RWC-1 is based on the reduced inter-processor communication architecture (RICA), in which communications are combined with comp ..."
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this paper we describe the pipeline design and enhanced hardware for fast message handling in a RICA-1 processor, a processing element (PE) in the RWC-1 multiprocessor. The RWC-1 is based on the reduced inter-processor communication architecture (RICA), in which communications are combined
QUICK PIPING: A Fast, High-Level Model for Describing Processor Pipelines †
"... Responding to marketplace needs, today’s embedded processors must feature a flexible core that allows easy modification with fast time to market. In this environment, embedded processors are increasingly reliant on flexible support tools. This paper presents one such tool, called Quick Piping, a new ..."
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new, high-level formalism for modeling processor pipelines. Quick Piping consists of three primary components that together provide an easy-to-build, reusable processor description: Pipeline graphs—a new high-level formalism for modeling processor pipelines, pipe—a companion domain-specific language
Integrating Formal Verification and High-Level Processor Pipeline Synthesis
"... Abstract – When a processor implementation is synthesized from a specification using an automatic framework, this implementation still should be verified against its specification to ensure the automatic framework introduced no error. This paper presents our effort in integrating fully automated for ..."
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formal verification with a high-level processor pipeline synthesis framework. As an integral part of the pipeline synthesis, our framework also emits SMV models for checking the functional equivalence between the output pipelined processor implementation and its input non-pipelined specification. Well
Software pipelining: An effective scheduling technique for VLIW machines
, 1988
"... This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software pipelining, iterations of a loop in the source program are continuously initiated at constant intervals, before the preceding iterations complete. The advantage of software pipe ..."
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Cited by 581 (3 self)
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This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software pipelining, iterations of a loop in the source program are continuously initiated at constant intervals, before the preceding iterations complete. The advantage of software
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