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Virtual Private Caches

by Kyle J. Nesbit, James Laudon, James E. Smith - In Proc.of the 34th Intl. Symp. on Computer Architecture , 2007
"... Virtual Private Machines (VPM) provide a framework for Quality of Service (QoS) in CMP-based com-puter systems. VPMs incorporate microarchitecture mechanisms that allow shares of hardware resources to be allocated to executing threads. VPMs can thereby provide applications with an upper bound on exe ..."
Abstract - Cited by 76 (2 self) - Add to MetaCart
on execution time regardless of other thread activity. Virtual Private Caches (VPCs) are an important element of VPMs, and VPC hardware consists of two major components: the VPC Arbiters, which manage shared resource bandwidth, and the VPC Capacity Manager. Both the VPC Arbiter and VPC Capacity Manager provide

Massively parallel algorithms for private-cache chip multiprocessors

by Lars Arge, Michael T. Goodrich, Michael Nelson, Nodari Sitchinava , 2008
"... In this paper, we study massively parallel algorithms for private-cache chip multiprocessors (CMPs), focusing on methods for foundational problems that can scale to hundreds or even thousands of cores. By focusing on private-cache CMPs, we show that we can design efficient algorithms that need no ad ..."
Abstract - Cited by 29 (5 self) - Add to MetaCart
In this paper, we study massively parallel algorithms for private-cache chip multiprocessors (CMPs), focusing on methods for foundational problems that can scale to hundreds or even thousands of cores. By focusing on private-cache CMPs, we show that we can design efficient algorithms that need

Understanding the Limits of Capacity Sharing in CMP Private Caches

by Ahmad Samih, Anil Krishna, Yan Solihin
"... Abstract—Chip Multi Processor (CMP) systems present interesting design challenges at the lower levels of the cache hierarchy. Private L2 caches allow easier processor-cache design reuse, thus scaling better than a system with a shared L2 cache, while offering better performance isolation and lower a ..."
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Abstract—Chip Multi Processor (CMP) systems present interesting design challenges at the lower levels of the cache hierarchy. Private L2 caches allow easier processor-cache design reuse, thus scaling better than a system with a shared L2 cache, while offering better performance isolation and lower

A Low Overhead Coherence Solution for Multiprocessors with Private Cache Memories

by Mark S. Papamarcos, Janak H. Patel - In Proc. 11th ISCA , 1984
"... This paper presents a cache coherence solu-tion for multiprocessors organized around a single time-shared bus. The solution aims at reducing bus traffic and hence bus wait time. This in turn increases the overall processor utilization. Unlike most traditional high-performance coherence solutions, th ..."
Abstract - Cited by 167 (0 self) - Add to MetaCart
This paper presents a cache coherence solu-tion for multiprocessors organized around a single time-shared bus. The solution aims at reducing bus traffic and hence bus wait time. This in turn increases the overall processor utilization. Unlike most traditional high-performance coherence solutions

CloudCache: Expanding and Shrinking Private Caches

by Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
"... The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilization is becoming ever more important. Furthermore, available cores are expected to be underutilized due to the power wall an ..."
Abstract - Cited by 10 (0 self) - Add to MetaCart
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilization is becoming ever more important. Furthermore, available cores are expected to be underutilized due to the power wall

PERFORMANCE OF PRIVATE CACHE REPLACEMENT POLICIES FOR MULTICORE PROCESSORS

by Matthew Lentz, Manoj Franklin
"... Multicore processors have become ubiquitous, both in general-purpose and special-purpose applications. With the number of transistors in a chip continuing to increase, the number of cores in a processor is also expected to increase. Cache replacement policy is an important design parameter of a cach ..."
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with a multi-level cache hierarchy. Our experimental results show that for the private L1 caches, the LRU (Least Recently Used) replacement policy outperforms all of the other replacement policies. This is in contrast to what was observed in previous studies for the shared L2 cache. The results presented

  Shared  main  memory  Private  Cache Main Memory

by Kai Lampka (uu, Adam Lackorzynski (tud, Jonas Flodin (uu, Wang Yi (uu, Kai Lampka
"... (exhausIve ßà   empirically)   Design  and  implement  SW  mechanisms  (access protocols,   memory  mappings,   ….)   or  HW. 1. Introduc-on:   Microcontrollers  and  technical evoluIon 2. Shared  memory  in  mul-cores:   Cost  reducIon  vs Predictability 3. ..."
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(exhausIve ßà   empirically)   Design  and  implement  SW  mechanisms  (access protocols,   memory  mappings,   ….)   or  HW. 1. Introduc-on:   Microcontrollers  and  technical evoluIon 2. Shared  memory  in  mul-cores:   Cost  reducIon  vs Predictability 3. Controlling  applica-ons  at  run-‐-me:   Memory access control  for  hard  real-‐Ime  and  best-‐effort applicaIons running  in  parallel 4. Conclusion 3 Microcontrollers and  technical

I/O-Optimal Distribution Sweeping on Private-Cache Chip Multiprocessors

by Deepak Ajwani, Nodari Sitchinava, Norbert Zeh
"... Abstract—The parallel external memory (PEM) model has been used as a basis for the design and analysis of a wide range of algorithms for private-cache multi-core architectures. As a tool for developing geometric algorithms in this model, a parallel version of the I/O-efficient distribution sweeping ..."
Abstract - Cited by 3 (1 self) - Add to MetaCart
Abstract—The parallel external memory (PEM) model has been used as a basis for the design and analysis of a wide range of algorithms for private-cache multi-core architectures. As a tool for developing geometric algorithms in this model, a parallel version of the I/O-efficient distribution sweeping

Geometric Algorithms for Private-Cache Chip Multiprocessors (Extended Abstract)

by Deepak Ajwani, Norbert Zeh, Nodari Sitchinava
"... We study techniques for obtaining efficient algorithms for geometric problems on private-cache chip multiprocessors. We show how to obtain optimal algorithms for interval stabbing counting, 1-D range counting, weighted 2-D dominance counting, and for computing 3-D maxima, 2-D lower envelopes, and 2- ..."
Abstract - Cited by 5 (3 self) - Add to MetaCart
We study techniques for obtaining efficient algorithms for geometric problems on private-cache chip multiprocessors. We show how to obtain optimal algorithms for interval stabbing counting, 1-D range counting, weighted 2-D dominance counting, and for computing 3-D maxima, 2-D lower envelopes, and 2

I/O-optimal Algorithms for Orthogonal Problems for Private-Cache Chip Multiprocessors

by Deepak Ajwani, Nodari Sitchinava, Norbert Zeh
"... Abstract—The parallel external memory (PEM) model has been used as a basis for the design and analysis of a wide range of algorithms for the private-cache multi-core architectures. Recently a parallel version of the distribution sweeping framework was introduced to efficiently solve a number of orth ..."
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Abstract—The parallel external memory (PEM) model has been used as a basis for the design and analysis of a wide range of algorithms for the private-cache multi-core architectures. Recently a parallel version of the distribution sweeping framework was introduced to efficiently solve a number
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