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TABLE I Memory map of DES OPB bus device.

in On the Design of a Self-Reconfigurable SoPC Based Cryptographic Engine
by Tyrone Tai-on Kwok, Yu-kwong Kwok

Table 4.2: Resource utilization and timing analysis results for the longest path in Xilinx OPB- master core and custom-designed OPB-master interface implementations.

in RICE UNIVERSITY Design and Evaluation of FPGA-Based Gigabit-Ethernet/PCI Network Interface Card By
by Tinoosh Mohsenin 2004

TABLE I COMPARISON ACCORDING TO CRITERIA CATALOG OF SECTION II-C

in Dynamic Replica Management in Distributed Hash Tables
by Marcel Waldvogel, Paul Hurley, Daniel Bauer 2003
Cited by 5

Table II(c) : Results for sparse Euclidean graphs.

in unknown title
by unknown authors

Table 1-1: Summary of OPB master-only I/O

in unknown title
by unknown authors
"... In PAGE 14: ... By convention, registers in all OPB slave devices are aligned to word boundaries (lowest two address bits are quot;00 quot;), regardless of the size of the data in the register or the size of the peripheral. Master and Slave I/O: OPB masters adhere to the signal set shown in Table1 -1. OPB slaves adhere to the signal set shown in Table 1-2.... In PAGE 14: ... Master and Slave I/O: OPB masters adhere to the signal set shown in Table 1-1. OPB slaves adhere to the signal set shown in Table1 -2. Devices that are both master and slave adhere to the signal set shown in Table 1-3.... In PAGE 14: ... OPB slaves adhere to the signal set shown in Table 1-2. Devices that are both master and slave adhere to the signal set shown in Table1 -3. Page numbers referenced in the tables apply to both the OPB V2.... In PAGE 19: ... A more complex slave attachment can be used instead of left justification. OPB Comparison Table1 -4 illustrates the major embedded processor bus architectures used in Xilinx FPGAs and lists some of their characteristics. Each bus has different capabilities in terms of data transfer rates, multi-master capability, and data bursting.... ..."

Table 1-2: Summary of OPB Slave-only I/O

in unknown title
by unknown authors
"... In PAGE 14: ... By convention, registers in all OPB slave devices are aligned to word boundaries (lowest two address bits are quot;00 quot;), regardless of the size of the data in the register or the size of the peripheral. Master and Slave I/O: OPB masters adhere to the signal set shown in Table1 -1. OPB slaves adhere to the signal set shown in Table 1-2.... In PAGE 14: ... Master and Slave I/O: OPB masters adhere to the signal set shown in Table 1-1. OPB slaves adhere to the signal set shown in Table1 -2. Devices that are both master and slave adhere to the signal set shown in Table 1-3.... In PAGE 14: ... OPB slaves adhere to the signal set shown in Table 1-2. Devices that are both master and slave adhere to the signal set shown in Table1 -3. Page numbers referenced in the tables apply to both the OPB V2.... In PAGE 19: ... A more complex slave attachment can be used instead of left justification. OPB Comparison Table1 -4 illustrates the major embedded processor bus architectures used in Xilinx FPGAs and lists some of their characteristics. Each bus has different capabilities in terms of data transfer rates, multi-master capability, and data bursting.... ..."

Table 1-3: Summary of OPB Master/Slave Device I/O

in unknown title
by unknown authors
"... In PAGE 14: ... By convention, registers in all OPB slave devices are aligned to word boundaries (lowest two address bits are quot;00 quot;), regardless of the size of the data in the register or the size of the peripheral. Master and Slave I/O: OPB masters adhere to the signal set shown in Table1 -1. OPB slaves adhere to the signal set shown in Table 1-2.... In PAGE 14: ... Master and Slave I/O: OPB masters adhere to the signal set shown in Table 1-1. OPB slaves adhere to the signal set shown in Table1 -2. Devices that are both master and slave adhere to the signal set shown in Table 1-3.... In PAGE 14: ... OPB slaves adhere to the signal set shown in Table 1-2. Devices that are both master and slave adhere to the signal set shown in Table1 -3. Page numbers referenced in the tables apply to both the OPB V2.... In PAGE 19: ... A more complex slave attachment can be used instead of left justification. OPB Comparison Table1 -4 illustrates the major embedded processor bus architectures used in Xilinx FPGAs and lists some of their characteristics. Each bus has different capabilities in terms of data transfer rates, multi-master capability, and data bursting.... ..."

Table 8-4: OPB Memory Map (unused areas not shown) Physical Address

in unknown title
by unknown authors

Table 2: IIC-C (CBM) relative IPC as the cache size is increased. IPC is relative to that of an IIC of the same size. The aver- age is for all 26 benchmarks.

in A Compressed Memory Hierarchy Using an Indirect Index Cache
by Erik G. Hallnor, Steven K. Reinhardt 2004
"... In PAGE 10: ...3.4 Sensitivity Analysis Table2 presents the relative performance of the IIC-C as we increase the cache Table 2: IIC-C (CBM) relative IPC as the cache size is increased. IPC is relative to that of an IIC of the same size.... ..."
Cited by 6

Table 2: IIC-C (CBM) relative IPC as the cache size is increased. IPC is relative to that of an IIC of the same size. The aver- age is for all 26 benchmarks.

in A Compressed Memory Hierarchy Using an Indirect Index Cache
by Erik G. Hallnor, Steven K. Reinhardt 2004
"... In PAGE 10: ...3.4 Sensitivity Analysis Table2 presents the relative performance of the IIC-C as we increase the cache Table 2: IIC-C (CBM) relative IPC as the cache size is increased. IPC is relative to that of an IIC of the same size.... ..."
Cited by 6
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