This paper shows new algorithms and the implementations of image reorganization for EAN/QR barcodes in mobile phones. The mobile phone system used here consists of a camera, mobile application processor, digital signal processor (DSP), and display device, and the source image is captured by the embedded camera device. The introduced algorithm is based on the code area found by four corners detection for 2D barcode and spiral scanning for 1D barcode using the embedded DSP. This algorithm is robust for practical situations and the DSP has god enough perfor4mance for the real-time recognition of the codes. The performance of our image processing is 66.7 frames / sec for EAN code and 14.1 frames / sec for QR code image processing, and this is sufficient performance for practical use. The released mobile phone had performance of 5-10 frames / sec including OS and subsystem overheads.

In this paper, we describe a design methodology and tools for NEC Electronics ’ structured ASIC, Instant Silicon Solution Platform (ISSP), which is being developed to fill the gap between FPGAs and standard cell-based ASICs. The ISSP has a unique regular-fabric architecture designed to achieve both

In [1] three principal themes are identified by the UK MoD (Ministry of Defence) in order to deliver the vision of NEC (Network Enabled Capability): Networks, People and Information. It is the security of information, which is discussed in this article. The drive towards NEC is due to many factors

Techniques for executing system verification using an FPGA-based prototyping board are being applied widely be-fore the actual chip fabrication process is completed. For the verification of the next-generation processors to succeed the V850E1 series, NEC Electronics has recently started the in

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multicontext

Abstract — In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics ’ DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power

than a traditional paper record. n JAMIA. 1996;3:i39-148. One purpose of electronic medical records (EMRs) is to increase the accessibility and sharing of health rec-ords among authorized individuals. Privacy of infor-mation collected during health care processes is nec-essary because of significant

We propose a cryptographic accelerator for IPsec by using the NEC electronics ’ Dynamically Reconfig-urable Processor (DRP). In our system, an embedded processor and DRP are integrated in a System-on-a-Chip (SoC) and multiple cryptographic tasks can be accelerated by DRP. Moreover, the virtual

(Multiple Input Signature Register) as DFT (Design For Testability). This method can reduce test execution time while maintaining the high rate of fault coverage. Evaluation of the proposed method examined on DRP-1, a coarsegrained Dynamically Reconfiguration Processor developed by NEC electronics in 2002

the processing intensive tasks, namely the reversible discrete wavelet transform (DWT), arithmetic encoding, and a portion of coefficient bit modeling with the reconfigurable processor DRP-1 by NEC Electronics. By using the DRP-1, performance of DWT, arithmetic encoding, and a portion of coefficient bit modeling