control and data speculation to execute such tasks in parallel. Inter-task register dependencies represent register communication in the architecture. The two primary issues in register communi-cation for a Multiscalar processor are correctness and performance. Not only must proper values be directed from

The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential programs without impeding improvements in clock speeds. The main goal of this paper is to understand the key

needed to avoid a mis-speculation. Experimental results evaluating the effectiveness of the proposed techniques are presented within the context of a Multiscalar processor. 1

circuits imply reduced design tolerances and hence increased failure probability. Conventional hardware redundancy techniques for desired reliability in computation may severely limit the performance of such high performance processors. Hence we need to study novel methods to exploit the inherent

for a superscalar processor. The paper also shows the ARB’s applica-tion in a multiscalar processor. Instruction-level parallel (ILP) processors boost performance by forming an instruction execution schedule, either statically or dynamically, in which the instructions are executed in an order

-critical loads and the criticality based thread-prediction for reducing useless computations and energy consumption. Experimental results showing break-up of critical instructions and effectiveness of proposed techniques in reducing energy consumption are presented in the context of multiscalar processor

There has been a growing interest in the use of multithreading to speed up the execution of a single program. This paper highlights the problems involved in performing accurate branch predictions in singleprogram multi-threaded (SPMT) processors, where branches are predicted out of program order

to avoid a misspeculation. Experimental results evaluating the effectiveness of the proposed techniques are presented within the context of a Multiscalar processor. 1

Recently popularized hardware multithreading (HMT) architectures, such as SMT, Multiscalar and Terra do not provide flexible and efficient methods of thread management and synchronization in hardware. The α-Coral architecture is a tool for investigation of a more dynamic approach to thread

to avoid a misspeculation. Experimental results evaluating the effectiveness of the proposed techniques are presented within the context of a Multiscalar processor. 1 Introduction Speculative execution is an integral part of modern ILP processors, be they statically- or dynamically-scheduled designs