Results 1 - 10 of 158

Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures

by Richard Rashid, Avadis Tevanian, Michael Young, David Golub, Robert Baron, David Black, William Boloaky, Jonathan Chew - IEEE Transactions on Computers (TC , 1988
"... This paper describes the design and implementation of virtual memory management within the CMU Mach Operating System and the experiences gained by the Mach kernel group in porting that system to a variety of architectures. As of this writing, Maeh runs on more than half a dozen uniprocessors and mul ..."
Abstract - Cited by 190 (10 self) - Add to MetaCart
and multiprocessors including the VAX family of uniprocessors and multiprocessors, the IBM RT PC, the SUN 3, the Encore MultiMax, the Sequent Balance 21000 and several experimental computers. Although these systems vary considerably in the kind of hardware support for memory management they provide, the machine

Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors

by Anant Agarwal, John Kubiatowicz, David Kranz, Beng-Hong Lim, Donald Yeung, Godfrey D'Souza, Mike Parkin - IEEE MICRO , 1993
"... Sparcle is a processor chip developed jointly by MIT, LSI Logic, and SUN Microsystems, by evolving an existing RISC architecture towards a processor suited for large-scale multiprocessors. Sparcle supports three multiprocessor mechanisms: fast context switching, fast, user-level message handling, a ..."
Abstract - Cited by 112 (21 self) - Add to MetaCart
Sparcle is a processor chip developed jointly by MIT, LSI Logic, and SUN Microsystems, by evolving an existing RISC architecture towards a processor suited for large-scale multiprocessors. Sparcle supports three multiprocessor mechanisms: fast context switching, fast, user-level message handling

Multiprocessors Should Support Simple Memory Consistency Models

by Mark D. Hill , 1998
"... Many future computers will be shared-memory multiprocessors. These hardware systems must define for software the allowable behavior of memory. A reasonable model is sequential consistency (SC), which makes a shared memory multiprocessor behave like a multiprogrammed uniprocessor. Since SC appears to ..."
Abstract - Cited by 97 (1 self) - Add to MetaCart
aggressively relax the order among all normal reads and writes (weak ordering, release consistency, DEC Alpha, IBM PowerPC, and Sun RMO). This paper argues that multiprocessors should implement SC or, in some cases, a model that just relaxes the ordering from writes to reads. I argue against using

Interprocessor Communication in Chip Multiprocessors

by Magnus Jahre, Ultrasparc T [mic Abstract
"... Spring 2006The photo on the title page shows the die of Sun Microsystem’s 8-core chip multiprocessor ..."
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Spring 2006The photo on the title page shows the die of Sun Microsystem’s 8-core chip multiprocessor

Adaptive Aggregation on Chip Multiprocessors

by John Cieslewicz, Kenneth A. Ross , 2007
"... The recent introduction of commodity chip multiprocessors requires that the design of core database operations be carefully examined to take full advantage of on-chip parallelism. In this paper we examine aggregation in a multi-core environment, the Sun UltraSPARC T1, a chip multiprocessor with eigh ..."
Abstract - Cited by 33 (4 self) - Add to MetaCart
The recent introduction of commodity chip multiprocessors requires that the design of core database operations be carefully examined to take full advantage of on-chip parallelism. In this paper we examine aggregation in a multi-core environment, the Sun UltraSPARC T1, a chip multiprocessor

SunOS Multi-thread Architecture

by M. L. Powell, S. R. Kleiman, S. Barton, D. Shah, D. Stein, M. Weeks - In Proceedings of the Winter 1991 USENIX Conference , 1991
"... We describe a model for multiple threads of control within a single UNIX process. The main goals are to provide extremely lightweight threads and to rationalize and extend the UNIX Application Programming Interface for a multi-threaded environment. The threads are intended to be sufficiently lightw ..."
Abstract - Cited by 58 (1 self) - Add to MetaCart
allows the programmer to separate logical (program) concurrency from the required real concurrency, which is relatively costly, and to control both within a single programming model. Introduction The reasons for supporting multiple threads of control in SunOS fall into two categories, those motivated

A Stream Chip-Multiprocessor for

by Ravi Kiran Karanam, Arun Ravindran, Arindam Mukherjee
"... Abstract- Bioinformatics applications such as gene and protein sequence matching algorithms are characterized by the need to process large amounts of data. While uni-processor performance growth is slowing due to an increasing gap between processor and memory speeds and a saturation of processor clo ..."
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clock frequencies, Genbank data is doubling every 15 months. With the advent of chip multiprocessor systems, great improvements in processor performance could potentially be achieved by taking advantage of the high interprocessor communication bandwidth and new models of programming. We propose a stream

Sun Microsystems

by Michel Dubois, Christoph Scheurich, Fayc A. Brigs
"... ultiprocessors, especially those constructed of relatively low-cost microprocessors, offer a cost-effective solution to the continually increasing need for computing power and speed. These systems can be designed either to maximize the throughput of many jobs or to speed up the execution of a single ..."
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single job; they are respectively called throughput-oriented and speeduporiented multiprocessors. In the first type of system, jobs are distinct from each other and execute as if they were running on different uniprocessors. In the second type an application is partitioned into a set

Sun Microsystems

by Sudheendra Hangal, Durgam Vahia, Chaiyasit Manovit, Juin-yeu Joseph Lu, Sridhar Narayanan
"... In this paper, we describe TSOtool, a program to check the behavior of the memory subsystem in a shared memory multiprocessor. TSOtool runs pseudo-randomly generated programs with data races on a system compliant with the Total Store Order (TSO) memory consistency model; it then checks the results o ..."
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In this paper, we describe TSOtool, a program to check the behavior of the memory subsystem in a shared memory multiprocessor. TSOtool runs pseudo-randomly generated programs with data races on a system compliant with the Total Store Order (TSO) memory consistency model; it then checks the results

, Guangyu Sun,

by Xiaoxia Wu, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita Das, Jian Li
"... The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a promising and scalable solution for interconnecting the cores in CMPs, however it consumes significant portion of the to-ta ..."
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The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a promising and scalable solution for interconnecting the cores in CMPs, however it consumes significant portion of the to
Results 1 - 10 of 158