the rate of improvement in DRAM memory speed--- each is improving exponentially, but the exponent for microprocessors is substantially larger than that for DRAMs. The difference between diverging exponentials also grows exponentially; so, although the disparity between processor and memory speed is already

The memory wall is the predicted situation where improvements to processor speed will be masked by the much slower improvement in dynamic random access (DRAM) memory speed. Since the prediction was made in 1995, considerable progress has been made in addressing the memory wall. There have been

The memory wall is the predicted situation where improvements to processor speed will be masked by the much slower improvement in dynamic random access (DRAM) memory speed. Since the prediction was made in 1995, considerable progress has been made in addressing the memory wall. There have been

Overhead of memory accesses limits the performance of packet processing applications. To overcome this bottleneck, today’s network processors can utilize a wide-range of mechanisms—such as multi-level memory hierarchy, wide-word accesses, special-purpose result-caches, asynchronous memory

The last line of defense in the cache hierarchy before going to off-chip memory is very critical in chip multiprocessors (CMPs) from both the performance and power perspectives. This paper investigates different organizations for this last line of defense (assumed to be L2 in this paper) towards

is not limited by the computation resources, but by the overhead in data movement. In fact, adding more cores or threads is likely to harm performance due to contention in the memory system. It is therefore important to improve data management to either reduce or tolerate data movement and associated latencies

Not many 19-year-olds set off on a national campaign to save lives during their freshman year in college. But Dieter Schmitz is everything but a normal 19 year-old. Schmitz, a San Diego State hospitality and tourism management freshman, who many know from the hit MTV reality show, “Laguna Beach: The Real Orange County,” has used his fame to found and create his own non-profit, Running Home 4 Teens. RH4T has caught the nation’s attention and support, all while benefiting SAVE.

. Current trends indicate improving memory bandwidth and stagnant memory latency. This makes the new algorithm especially important for future computer architectures. In addition, we believe this "memory wall" will soon force a redesign of other common algorithms of symbolic algebra.

Managing the memory wall is critical for massively par-allel FPGA applications where data-sets are large and exter-nal memory must be used. We demonstrate that a soft vector processor can efficiently stream data from external memory whilst running computation in parallel. A non-trivial neu

Coset enumeration, like Gröbner bases, is a notoriously difficult algorithm to parallelize. We demonstrate a successful shared memory parallelization achieving a 7 times speedup on an Origin 2000 CC-NUMA computer using 16 CPUs. We take as a testbed, an enumeration of Lyons's group (8