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Results 1 - 10
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104
Reducing Web Latency: the Virtue of Gentle Aggression
"... To serve users quickly, Web service providers build infrastruc-ture closer to clients and use multi-stage transport connections. Although these changes reduce client-perceived round-trip times, TCP’s current mechanisms fundamentally limit latency improve-ments. We performed a measurement study of a ..."
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To serve users quickly, Web service providers build infrastruc-ture closer to clients and use multi-stage transport connections. Although these changes reduce client-perceived round-trip times, TCP’s current mechanisms fundamentally limit latency improve-ments. We performed a measurement study of a
Predicting short-transfer latency from TCP arcana: extended version
, 2005
"... In some contexts it may be useful to predict the latency for short TCP transfers. For example, a Web server could auto-matically tailor its content depending on the network path to each client, or an “opportunistic networking ” application could improve its scheduling of data transfers. Several tech ..."
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Cited by 16 (2 self)
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In some contexts it may be useful to predict the latency for short TCP transfers. For example, a Web server could auto-matically tailor its content depending on the network path to each client, or an “opportunistic networking ” application could improve its scheduling of data transfers. Several
Microarchitecture optimizations for exploiting memory-level parallelism
- In ISCA-31
, 2004
"... The performance of memory-bound commercial applications such as databases is limited by increasing memory latencies. In this paper, we show that exploiting memory-level parallelism (MLP) is an effective approach for improving the performance of these applications and that microarchitecture has a pro ..."
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Cited by 97 (3 self)
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The performance of memory-bound commercial applications such as databases is limited by increasing memory latencies. In this paper, we show that exploiting memory-level parallelism (MLP) is an effective approach for improving the performance of these applications and that microarchitecture has a
Automatic thread extraction with decoupled software pipelining
- In Proceedings of the 38th IEEE/ACM International Symposium on Microarchitecture
, 2005
"... {ottoni, ram, astoler, august}@princeton.edu Abstract Until recently, a steadily rising clock rate and otheruniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance fora wide range of applications. Current difficulties in maintaining this trend ..."
Abstract
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Cited by 101 (18 self)
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this trend have lead microprocessor manufacturersto add value by incorporating multiple processors on a chip. Unfortunately, since decades of compiler research have notsucceeded in delivering automatic threading for prevalent code properties, this approach demonstrates no improve-ment for a large class
GeoWeight: Internet host geolocation based on a probability model for latency measurements
- In Pro- of the Thirty-Third Australasian Conference on Computer Science, volume 102 of ACSC ’10
, 2010
"... Knowing the geographical location of an Internet host is of importance to many of today’s Internet services. In this paper we focus on geolocating Internet hosts based purely on latency measurements. Existing la-tency measurement-based geolocation techniques use the observed latencies from multiple ..."
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Cited by 4 (0 self)
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of the target being in that sub-region; a higher weight indicating a more probable region. By considering latency measure-ments from multiple landmarks and computing the resultant weights of overlapping regions a better con-strained target region can be obtained. This paper presents the GeoWeight algorithm
RepFlow on node.js: Cutting Tail Latency in Data Center Networks at the Applications Layer
"... Low latency, especially at the tail, is increasingly demanded by interactive applications in data center networks. To im-prove tail latency, existing approaches require modifications to switch hardware and/or end-host stacks, making them dif-ficult to be deployed. We present the design, implementa-t ..."
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Low latency, especially at the tail, is increasingly demanded by interactive applications in data center networks. To im-prove tail latency, existing approaches require modifications to switch hardware and/or end-host stacks, making them dif-ficult to be deployed. We present the design
FlowBender: Flow-level Adaptive Routing for Improved Latency and Throughput in Datacenter Networks
"... Datacenter networks provide high path diversity for traffic between machines. Load balancing traffic across these paths is important for both, latency- and throughput-sensitive ap-plications. The standard load balancing techniques used to-day obliviously hash a flow to a random path. When long flows ..."
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Cited by 3 (1 self)
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data centers today. (5) Is very robust and simple to tune. We evaluate FlowBender using both simulations and a real testbed implementation, and show that it improves average and tail latencies significantly compared to state of the art techniques without incurring the significant overhead
OpenSample: A Low-latency, Sampling-based Measurement Platform for Commodity SDN
"... Abstract—In this paper we propose, implement and evaluate OpenSample: a low-latency, sampling-based network measure-ment platform targeted at building faster control loops for software-defined networks. OpenSample leverages sFlow packet sampling to provide near–real-time measurements of both net-wor ..."
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Abstract—In this paper we propose, implement and evaluate OpenSample: a low-latency, sampling-based network measure-ment platform targeted at building faster control loops for software-defined networks. OpenSample leverages sFlow packet sampling to provide near–real-time measurements of both net
A stateless, content-directed data prefetching mechanism
, 2002
"... Although central processor speeds continues to improve, improve-ments in overall system performance are increasingly hampered by memory latency, especially for pointer-intensive applications. To counter this loss of performance, numerous data and instruc-tion prefetch mechanisms have been proposed. ..."
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Cited by 61 (0 self)
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Although central processor speeds continues to improve, improve-ments in overall system performance are increasingly hampered by memory latency, especially for pointer-intensive applications. To counter this loss of performance, numerous data and instruc-tion prefetch mechanisms have been proposed
A Trace Cache Microarchitecture and Evaluation
- IEEE Transactions on Computers
, 1999
"... As the instruction issue width of superscalar proces-sors increases, instruction fetch bandwidth requirements will also increase. It will eventually become necessary to fetch multiple basic blocks per clock cycle. Conventional in-struction caches hinder this effort because long instruction sequences ..."
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Cited by 55 (3 self)
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. The microarchitecture provides high instruc-tion fetch bandwidth with low latency by explicitly sequenc-ing through the program at the higher level of traces, both in terms of (1) control flow prediction and (2) instruction supply. For the SPEC95 integer benchmarks, trace-level se-quencing improves performance from 15
Results 1 - 10
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104
