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2,274
MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems
"... Over the last decade, significant advances have been made in compilation technology for capitalizing on instruction-level parallelism (ILP). The vast majority of ILP compilation research has been conducted in the context of generalpurpose computing, and more specifically the SPEC benchmark suite. At ..."
Abstract
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Cited by 966 (22 self)
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Over the last decade, significant advances have been made in compilation technology for capitalizing on instruction-level parallelism (ILP). The vast majority of ILP compilation research has been conducted in the context of generalpurpose computing, and more specifically the SPEC benchmark suite
Combining Branch Predictors
, 1993
"... One of the key factors determining computer performance is the degree to which the implementation can take advantage of instruction-level paral-lelism. Perhaps the most critical limit to this parallelism is the presence of conditional branches that determine which instructions need to be executed ne ..."
Abstract
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Cited by 629 (0 self)
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One of the key factors determining computer performance is the degree to which the implementation can take advantage of instruction-level paral-lelism. Perhaps the most critical limit to this parallelism is the presence of conditional branches that determine which instructions need to be executed
Instruction-Level Steganography
"... Abstract. Trigger-based malware is designed to remain dormant and undetected unless a specific trigger occurs. Such behavior occurs in preva-lent threats such as backdoors and environment-dependent (targeted) malware. Currently, trigger-based malicious code is often hidden in rarely exercised code p ..."
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Abstract. Trigger-based malware is designed to remain dormant and undetected unless a specific trigger occurs. Such behavior occurs in preva-lent threats such as backdoors and environment-dependent (targeted) malware. Currently, trigger-based malicious code is often hidden in rarely exercised code
Pin: building customized program analysis tools with dynamic instrumentation
- IN PLDI ’05: PROCEEDINGS OF THE 2005 ACM SIGPLAN CONFERENCE ON PROGRAMMING LANGUAGE DESIGN AND IMPLEMENTATION
, 2005
"... Robust and powerful software instrumentation tools are essential for program analysis tasks such as profiling, performance evaluation, and bug detection. To meet this need, we have developed a new instrumentation system called Pin. Our goals are to provide easy-to-use, portable, transparent, and eff ..."
Abstract
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Cited by 991 (35 self)
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, and efficient instrumentation. Instrumentation tools (called Pintools) are written in C/C++ using Pin’s rich API. Pin follows the model of ATOM, allowing the tool writer to analyze an application at the instruction level without the need for detailed knowledge of the underlying instruction set. The API
Formal Specification and Simulation of Instruction-Level Parallelism
- In Proceedings of the 1994 European Design Automation Conference
, 1994
"... In this paper we show how to formally specify and simulate the high-level instruction timing properties of RISC/Superscalar instruction set processors. We illustrate the technique using a hypothetical processor that includes many features of commercial processors including delayed loads and branches ..."
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Cited by 6 (4 self)
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In this paper we show how to formally specify and simulate the high-level instruction timing properties of RISC/Superscalar instruction set processors. We illustrate the technique using a hypothetical processor that includes many features of commercial processors including delayed loads
Automatic Instruction-Level Software-Only Recovery Methods
- In International Conference on Dependable Systems and Networks (DSN’06
, 2006
"... As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically addressed reliability issues by adding redundant hardware, but these techniques are often too expensive to be used widely. ..."
Abstract
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Cited by 34 (1 self)
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. In this paper, we present the concept, implementation, and evaluation of automatic, instruction-level, software-only recovery techniques, as well as various specific techniques representing different trade-offs between reliability and performance. Our evaluation shows that these techniques fulfill the promises
Exploiting Instruction-Level Parallelism: A constructive approach
, 1998
"... havioral--level specification of the digital system into an architecture consisting of a data path and a control unit. Emerging design problems are prompting the utilization of instruction--level parallelism (ILP), traditionally an object of parallelizing compilers, for the synthesis of digital sys ..."
Abstract
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Cited by 6 (2 self)
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havioral--level specification of the digital system into an architecture consisting of a data path and a control unit. Emerging design problems are prompting the utilization of instruction--level parallelism (ILP), traditionally an object of parallelizing compilers, for the synthesis of digital
High-Level Timing Specification of Instruction-Level Parallel Processors
, 1993
"... In modern instruction set processors, the temporal and concurrent properties of the instructions are often visible to the user of the processor. To use the processor as efficiently as possible, the user needs this information. Consequently, this instruction-level parallelism should be included in a ..."
Abstract
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Cited by 2 (0 self)
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In modern instruction set processors, the temporal and concurrent properties of the instructions are often visible to the user of the processor. To use the processor as efficiently as possible, the user needs this information. Consequently, this instruction-level parallelism should be included
Microprocessor Design Verification
- Journal of Automated Reasoning
, 1989
"... The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32-bit general purpose, von Neumann processor whose design-level (gate-level) specification has been verified with respect to its instruction-level specification ..."
Abstract
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Cited by 60 (3 self)
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The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32-bit general purpose, von Neumann processor whose design-level (gate-level) specification has been verified with respect to its instruction-level
Simulating the power consumption of large-scale sensor network applications
- In Sensys
, 2004
"... Developing sensor network applications demands a new set of tools to aid programmers. A number of simulation environments have been developed that provide varying degrees of scalability, realism, and detail for understanding the behavior of sensor networks. To date, however, none of these tools have ..."
Abstract
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Cited by 327 (4 self)
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to estimate the number of CPU cycles executed by each node, eliminating the need for expensive instruction-level simulation of sensor nodes. PowerTOSSIM includes a detailed model of hardware energy consumption based on the Mica2 sensor node platform. Through instrumentation of actual sensor nodes, we
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2,274
