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365
Streaming Dynamic Coarse-Grained CPU/GPU Workloads with Heterogeneous Pipelines in FastFlow
"... Abstract—Software pipelines permit the decomposition of a repetitive sequential process into a succession of distinguishable sub-processes called stages, each of which can be concurrently executed on a distinct processing element. This paper presents a heterogeneous streaming pipeline implementation ..."
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Cited by 1 (0 self)
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Abstract—Software pipelines permit the decomposition of a repetitive sequential process into a succession of distinguishable sub-processes called stages, each of which can be concurrently executed on a distinct processing element. This paper presents a heterogeneous streaming pipeline
Pipeline
"... rival scale-up. • Heterogeneity is increasing: applications are adopting CPU and GPU / data-parallel regions. � Programming parallel & heterogeneous is hard. (Also, multi-platform/configuration is important) Software: • Coherence matters: processing groupings of coherent ‘work ’ is efficient. • ..."
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rival scale-up. • Heterogeneity is increasing: applications are adopting CPU and GPU / data-parallel regions. � Programming parallel & heterogeneous is hard. (Also, multi-platform/configuration is important) Software: • Coherence matters: processing groupings of coherent ‘work ’ is efficient
Pipelining broadcasts on heterogeneous platforms
, 2005
"... In this paper, we consider the communications involved by the execution of a complex application, deployed on a heterogeneous platform. Such applications extensively use macrocommunication schemes, for example, to broadcast data items. Rather than aiming at minimizing the execution time of a single ..."
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Cited by 36 (15 self)
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single broadcast, we focus on the steady-state operation. We assume that there is a large number of messages to be broadcast in pipeline fashion, and we aim at maximizing the throughput, i.e., the (rational) number of messages which can be broadcast every time-step. We target heterogeneous platforms
Pipelining and Transposing Heterogeneous Array Designs
- Journal of VLSI Signal Processing
, 1993
"... Abstract. This paper describes a scheme for representing heterogeneous array circuits, in particular those which have been optimized by pipelining or by transposition. Equations for correctness-preserving transformations of these parametric representations are presented. The method is illustrated on ..."
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Cited by 1 (1 self)
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Abstract. This paper describes a scheme for representing heterogeneous array circuits, in particular those which have been optimized by pipelining or by transposition. Equations for correctness-preserving transformations of these parametric representations are presented. The method is illustrated
Dual-pipeline heterogeneous asip design
- In Proceedings of CODES + ISSS
, 2004
"... In this paper we demonstrate the feasibility of a dual pipeline Application Specific Instruction Set Processor. We take a C program and create a target instruction set by compiling to a basic instruction set, from which some instructions are merged, while others discarded. Based on the target instru ..."
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Cited by 1 (1 self)
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instruction set, parallelism of the application program is analyzed and two unique instruction sets are generated for a heterogeneous dual-pipeline processor. The dual pipe processor is created by making two unique ASIPs (VHDL descriptions) utilizing the ASIP-Meister Tool Suite, and fusing the two VHDL
Design Methodology for Pipelined Heterogeneous Multiprocessor System
, 2007
"... Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g. SMP) and application specific architectures (i.e. DSP, ASIC). ASIPs have emerged as a viable alternative to conve ..."
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Cited by 17 (4 self)
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to conventional processing entities (PEs) due to its configurability and programmability. In this work, we introduce a heterogeneous multi-processor system using ASIPs as processing entities in a pipeline configuration. A streaming application is taken and manually broken into a series of algorithmic stages (each
Published In Heterogeneous Latch-based Asynchronous Pipelines
"... We present a technique to automatically synthesize hetero-geneous asynchronous pipelines by combining two different latching styles: normally open D-latches [19] for high per-formance and self-resetting D-latches [5] for low power. The former is fast but results in high power consumption due to data ..."
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We present a technique to automatically synthesize hetero-geneous asynchronous pipelines by combining two different latching styles: normally open D-latches [19] for high per-formance and self-resetting D-latches [5] for low power. The former is fast but results in high power consumption due
ABSTRACT Dual-Pipeline Heterogeneous A IP Design
"... merged, while others discarded. Based on the target instruction set, parallelism of the application program is analyzed and two unique instruction sets are generated for a heterogeneous dual-pipeline processor. The dual pipe processor is created bv makine two uniaue ASIPs (VHDL descrintionsi I. ~ Ap ..."
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merged, while others discarded. Based on the target instruction set, parallelism of the application program is analyzed and two unique instruction sets are generated for a heterogeneous dual-pipeline processor. The dual pipe processor is created bv makine two uniaue ASIPs (VHDL descrintionsi I
On the Complexity of Mapping Pipelined Filtering Services on Heterogeneous Platforms
, 2008
"... In this paper, we explore the problem of mapping filtering services on large-scale heterogeneous platforms. Two important optimization criteria should be considered in such a framework. The period, which is the inverse of the throughput, measures the rate at which data sets can enter the system. The ..."
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Cited by 1 (1 self)
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In this paper, we explore the problem of mapping filtering services on large-scale heterogeneous platforms. Two important optimization criteria should be considered in such a framework. The period, which is the inverse of the throughput, measures the rate at which data sets can enter the system
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