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Application of task concurrency management on dynamically reconfigurable hardware platforms

Modeling and simulation plays an important role in the development of computer systems. This research work focuses on modeling general computer hardware platforms using the Discrete Event system Specification (DEVS) modeling formalism, and mapping these models onto the High Level Architecture (HLA

Abstract Sorting is a common problem in computer science. There are a lot of well-known sorting algorithms created for sequential execution on a single processor. Recently, many-core and multi-core platforms have enabled the creation of wide parallel algorithms. We have standard processors

In the domain of spatial computing, it appears that platforms based on either reconfigurable datapath units or on hybrid microprocessor/logic cell organizations are in the ascendancy as they appear to offer the most efficient means of providing resources across the greatest range of hardware

Abstract — The paper describes hardware solutions for the IEEE 802.11 MAC (Medium Access Control) layer and IEEE 802.11a digital baseband in an RF-MIMO WLAN transceiver that performs the signal combining in the analogue domain. Architecture and implementation details of the MAC processor including

. This paper explores the impact of anticipated communication services for future wireless communication systems on the evolution of microelectronics for wireless terminals. A roadmap is presented which predicts the hardware/software split of future software defined radio terminals (SDR terminals

Implementing quaternion based AHRS on a MEMS

Lecture material and readings are posted at

Abstract not found