Tools
Sorted by:
Try your query at:
 |
 |
 |
 |
 |
 |
Results 1 -
2 of
2
Verification of the Futurebus+ Cache Coherence Protocol
, 1995
"... We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+ standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous ..."
Abstract
-
Cited by 104 (16 self)
- Add to MetaCart
and unambiguous model of the protocol that should be useful both to the Futurebus+ Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+ boards.
Bi-directional optical backplane bus for general purpose multi-processor board-toboard optoelectronic interconnects
- J. Lightwave Technol
, 1995
"... Absfract- We report for the first time a bidirectional opti-cal backplane bus for a high performance system containing nine multi-chip module (MCM) boards, operating at 632.8 and 1300 nm. The backplane bus reported here employs arrays of multiplexed polymer-based waveguide holograms in conjunction w ..."
Abstract
-
Cited by 14 (7 self)
- Add to MetaCart
Absfract- We report for the first time a bidirectional opti-cal backplane bus for a high performance system containing nine multi-chip module (MCM) boards, operating at 632.8 and 1300 nm. The backplane bus reported here employs arrays of multiplexed polymer-based waveguide holograms in conjunction
