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High-level power analysis for multi-core chips, in: CASES’06
- Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems
, 2006
"... Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs), with on-chip networks increasingly becoming the de facto communication fabric between cores as the demand for on-chip ..."
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Cited by 12 (0 self)
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various power-performance tradeoffs for future multi-core chips.
ABSTRACT High-Level Power Analysis for Multi-Core Chips
"... Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs), with on-chip networks increasingly becoming the de facto communication fabric between cores as the demand for on-chip ..."
When choice is demotivating: can one desire too much of a good thing
- Journal of Personality and Social Psychology
, 2000
"... Current psychological theory and research affirm the positive affective and motivational consequences of having personal choice. These findings have led to the popular notion that the more choice, the better--that the human ability omanage, and the human desire for, choice isunlimited. Findings from ..."
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Cited by 438 (12 self)
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of options had been limited. Implications for future research are discussed. Ne quid nimis. (In all things moderation.)--Publius Terentius Afer (Terence), c. 171 B.C. It is a common supposition in modern society that the more choices, the better--that the human ability to manage, and the human desire for
Impact of parameter variations on multi-core chips
- In Workshop on Architectural Support for Gigascale Integration
, 2006
"... Increasing variability during manufacturing and during runtime are projected for future generation microprocessors. This paper introduces a pre-RTL, architectural modeling methodology that incorporates the impact of manufacturing and runtime temperature variations on delay and power for both combina ..."
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Cited by 25 (1 self)
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will result in major leakage variation across multiple cores on a single chip. WID leakage variation can cause core-tocore leakage to differ by as much as 45%.
Collective Memory Transfers for Multi-Core Chips
"... Future performance improvements for microprocessors have shifted from clock frequency scaling towards increases in on-chip parallelism. Performance improvements for a wide variety of parallel applications require domain-decomposition of data arrays from a contiguous arrangement in memory to a tiled ..."
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Future performance improvements for microprocessors have shifted from clock frequency scaling towards increases in on-chip parallelism. Performance improvements for a wide variety of parallel applications require domain-decomposition of data arrays from a contiguous arrangement in memory to a tiled
Modeling the effect of technology trends on the soft error rate of combinational logic
, 2002
"... This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. Th ..."
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Cited by 374 (8 self)
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This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs
Performance Implications of Single Thread Migration on a Chip Multi-Core
- SIGARCH Computer Architecture News
, 2005
"... High performance multi-core processors are becoming an industry reality. Although multi-cores are suited for multithreaded and multi-programmed workloads, many applications are still mono-thread and multi-core performance with a single thread workload is an important issue. Furthermore, recent studi ..."
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Cited by 31 (6 self)
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studies suggest that performance, power and temperature considerations of future multi-cores may necessitate activity-migration between cores. Motivated by the above, this paper investigates the performance implications of single thread migration on a multi-core. Specifically, the study considers
McRT-STM: a High Performance Software Transactional Memory System for a Multi-Core Runtime
- In Proc. of the 11th ACM Symp. on Principles and Practice of Parallel Programming
, 2006
"... Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadl ..."
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Cited by 241 (14 self)
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that is part of McRT, an experimental Multi-Core RunTime. The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based conflict detection for C/C++ applications. The Mc
Exploring interconnections in multi-core architectures
, 2005
"... This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class of interconnect architectures. It shows that the design choices for the interconnect have significant effect on the rest o ..."
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Cited by 128 (6 self)
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of the chip, potentially consuming a significant fraction of the real estate and power budget. This research shows that designs that treat interconnect as an entity that can be independently architected and optimized would not arrive at the best multicore design. Several examples are presented showing
Multi-core Architectures and Streaming Applications
"... In this paper we focus on algorithms and reconfigurable multi-core architectures for streaming digital signal processing (DSP) applications. The multi-core concept has a number of advantages: (1) depending on the requirements more or fewer cores can be switched on/off, (2) the multi-core structure f ..."
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fits well to future process technologies, more cores will be available in advanced process technologies, but the complexity per core does not increase, (3) the multi-core concept is fault tolerant, faulty cores can be discarded and (4) multiple cores can be configured fast in parallel. Because in our
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