Results 1 - 10 of 3,567

Diagnosing multiple faults.

by Johan De Kleer , Brian C Williams - Artificial Intelligence, , 1987
"... Abstract Diagnostic tasks require determining the differences between a model of an artifact and the artifact itself. The differences between the manifested behavior of the artifact and the predicted behavior of the model guide the search for the differences between the artifact and its model. The ..."
Abstract - Cited by 808 (62 self) - Add to MetaCart
in the domain of troubleshooting digital circuits. This research makes several novel contributions: First, the system diagnoses failures due to multiple faults. Second, failure candidates are represented and manipulated in terms of minimal sets of violated assumptions, resulting in an efficient diagnostic

Paper Number Arc-fault Circuit Interrupters For Aerospace Applications

by John Brooks
"... Circuit Breakers have historically been the preferred protection for aerospace wiring. Present designs are based on technologies that are 40 years old. Advancements in electrical circuit protection introduced by the residential and commercial industries have been slow finding their way into aerospac ..."
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into aerospace applications. Ground fault circuit interrupters (GFCI) for personnel protection have been available in the home since the early 1970’s. GFCI can detect phase to ground arcs as low as six milliamps, but cannot detect series arcs or improve line to neutral fault trip times. Arc-fault detection

New Technology for Preventing Residential Electrical Fires: Arc-Fault Circuit Interrupters (AFCIs) By

by Douglas A. Lee, Andrew M. Trotta, William H. King
"... Abstract- A new generation of residential electrical branch circuit breakers that incorporates technology to detect and mitigate the effects of arcing faults is described. Fire loss estimates attributed to electrical wiring and the development of the arc-fault circuit interrupter for the prevention ..."
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Abstract- A new generation of residential electrical branch circuit breakers that incorporates technology to detect and mitigate the effects of arcing faults is described. Fire loss estimates attributed to electrical wiring and the development of the arc-fault circuit interrupter for the prevention

Delayed internet routing convergence

by Craig Labovitz, Abha Ahuja, Abhijit Bose, Farnam Jahanian - ACM SIGCOMM Computer Communication Review , 2000
"... Abstract—This paper examines the latency in Internet path failure, failover, and repair due to the convergence properties of interdomain routing. Unlike circuit-switched paths which exhibit failover on the order of milliseconds, our experimental mea-surements show that interdomain routers in the pac ..."
Abstract - Cited by 408 (5 self) - Add to MetaCart
Abstract—This paper examines the latency in Internet path failure, failover, and repair due to the convergence properties of interdomain routing. Unlike circuit-switched paths which exhibit failover on the order of milliseconds, our experimental mea-surements show that interdomain routers

Test pattern generation using Boolean satisfiability

by Tracy Larrabee - IEEE Transactions on Computer-Aided Design , 1992
"... Abstract-This article describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean diference between the unfaulted and faulted ..."
Abstract - Cited by 306 (14 self) - Add to MetaCart
Abstract-This article describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean diference between the unfaulted

Fault-tolerant quantum computation

by Peter W. Shor - In Proc. 37th FOCS , 1996
"... It has recently been realized that use of the properties of quantum mechanics might speed up certain computations dramatically. Interest in quantum computation has since been growing. One of the main difficulties in realizing quantum computation is that decoherence tends to destroy the information i ..."
Abstract - Cited by 264 (5 self) - Add to MetaCart
as originally believed. For any quantum computation with t gates, we show how to build a polynomial size quantum circuit that tolerates O(1 / log c t) amounts of inaccuracy and decoherence per gate, for some constant c; the previous bound was O(1 /t). We do this by showing that operations can be performed

Test Set Compaction Algorithms for Combinational Circuits

by Ilker Hamzaoglu, Janak H. Patel , 2000
"... This paper presents a new algorithm, Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. These algorithms together with the dynamic co ..."
Abstract - Cited by 156 (5 self) - Add to MetaCart
This paper presents a new algorithm, Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. These algorithms together with the dynamic

Local methods for localizing faults in electronic circuits

by Johan De Kleer - MIT Al Memo , 1976
"... The work described in this paper is part of an investigation of the issues Involved in making expert problem solving programs for engineering design and for maintenance of engineered systems. In particular, the paper focuses on the troubleshooting of electronic circuits. Only the individual properti ..."
Abstract - Cited by 25 (2 self) - Add to MetaCart
point. This is called a coincidence. In a faulted circuit, the assumptions made about components in the coinciding propagations can then be used to determine information about the faultiness of these components. In order for the program to deal with actual circuits, It handles errors in measurement

Fault Tolerance in VLSI Circuits

by Israel Koren, Adit D. Singh - IEEE Computer , 1990
"... this article we describe the defects that can occur when manufacturing VLSI 1Cs and the potential resulting faults, some commonly used restructuring techniques for avoiding defective components, and several defect-tolerant designs of memory ICs, logic ICs, and wafer-scale circuits. We will introduce ..."
Abstract - Cited by 15 (5 self) - Add to MetaCart
this article we describe the defects that can occur when manufacturing VLSI 1Cs and the potential resulting faults, some commonly used restructuring techniques for avoiding defective components, and several defect-tolerant designs of memory ICs, logic ICs, and wafer-scale circuits. We

On the Fault Testing for Reversible Circuits

by Satoshi Tayu, Shigeru Ito, Shuichi Ueno
"... Abstract. This paper shows that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit. We also show non-trivial lower bounds for the size of a minimum complete test set. 1 ..."
Abstract - Cited by 2 (1 self) - Add to MetaCart
Abstract. This paper shows that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit. We also show non-trivial lower bounds for the size of a minimum complete test set. 1
Results 1 - 10 of 3,567