coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example. ~rHE reasons for the practical impossibility of obtaining acomplete functional test for a large scale

We propose a new statistical technique for estimating fault coverage in combinational circuits. Our method requires fault-free simulation of a random sample of vectors from the test vector set. Fault coverage is computed from controllabilities and observabilities both defined as probabilities

basic ideas underlying the techniques for fault coverage analysis and assurance mainly developed in the context of protocol conformance testing based on finite state models. Special attention is paid to parameters which determine the testability of a given specification and influence the length of a

We propose a linear complexity method to estimate robust path delay fault coverage in digital circuits. We adopt a path counting scheme for a true-value simulator that uses flags for each signal line. These flags determine the new path delay faults detected by the simulated vector pair

This paper addresses the problem of evaluating the effectiveness of test sets to detect crosstalk defects in system-level interconnects and buses of deep submicron (DSM) chips. The fast and accurate estimation technique will enable: 1) evaluation of different existing tests, like functional, scan, logic built-in self-test (BIST), and delay tests, for effective testing of crosstalk defects in core-to-core interconnects and 2) development of crosstalk tests if the existing tests are not sufficient, thereby minimizing the cost of interconnect testing.

Modern tendencies of semiconductor industry devel-opment involve permanent decrease of silicon chip area, increase of quantity and various elements on area unit. Embedded memory elements make up the bulk of compo-

We present a new probabilistic fault coverage model that is accurate, simple, predictive, and easily integrated with the normal design flow of built-in self-test circuits. The parameters of the model are determined by fitting the fault simulation data obtained on an initial segment of the random

circuits can be analyzed through true-value simulation with random vectors [6]. In Section 3, we present a method of estimating p (x) from fault simulation. Fault Coverage. Fault coverage is the percentage (or fraction) of faults covered by test vectors. Generally, this coverage is over the set of all

With current approaches to partial scan, it is difficult, and often impossible, to achieve a specific level of fault coverage without returning to full scan. In this paper, we introduce a new formulation of the minimum scan chain assignment problem and propose an effective covering algorithm

Abstract – A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks