In this paper, we introduce an implementation of Ad-vanced Encryption Standard (AES) cryptography al-gorithm on the Dynamically Reconfigurable Processor (DRP)[1]. We have loaded it onto the DRP-1, the first

Designers of digital electronic systems face a fundamental tradeoff between flexibility and performance when they select computing elements. The available alternatives span a wide spectrum with general-purpose (GP) processors and application-specific integrated circuits (ASICs) at opposite ends. GP

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Abstract — In dynamically reconfigurable processors, different contexts as well as different data paths within one context usually vary in their execution time. Voltage scaling offers the ability to utilize this variation to reduce power consumption. In this paper, we propose a dual-VDD dynamically

Configuration with Self-configured Data Path (CSDP) is a high speed configuration data loading method for Dy-namically Reconfigurable Processors (DRPs). By using a prepared configuration data, a network for computation in DRPs can be used as a configuration data path when the computation is stalled

Abstract — In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics ’ DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power

Abstract — There are a growing number of recon-figurable architectures that combine the advantages of a hardwired implementation (performance, power con-sumption) with the advantages of a software solution (flexibility, time to market). Today, there are devices on the market that can be dynamically

We propose a cryptographic accelerator for IPsec by using the NEC electronics ’ Dynamically Reconfig-urable Processor (DRP). In our system, an embedded processor and DRP are integrated in a System-on-a-Chip (SoC) and multiple cryptographic tasks can be accelerated by DRP. Moreover, the virtual

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Abstract. Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing. For on-chip implementation, folding layout is also proposed. Evaluation results show that Fat H