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Dynamic partial reconfiguration in FPGAs
"... Abstract—Dynamic parital reconfigurable FPGAs offer new design space with a variety of benefits: reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones. This paper introduces a simple reconfigurable system and focuses on the advanta ..."
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Abstract—Dynamic parital reconfigurable FPGAs offer new design space with a variety of benefits: reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones. This paper introduces a simple reconfigurable system and focuses
Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems
"... Abstract—The dynamic partial reconfiguration technology enables an embedded system to adapt its hardware functionalities at run-time to changing environment conditions. However, reconfigurable hardware functions are still managed as conventional hardware devices, and the enhancement of system perfor ..."
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Cited by 3 (1 self)
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Abstract—The dynamic partial reconfiguration technology enables an embedded system to adapt its hardware functionalities at run-time to changing environment conditions. However, reconfigurable hardware functions are still managed as conventional hardware devices, and the enhancement of system
Dynamic Partial Reconfiguration in Low-Cost FPGAs
, 2013
"... Abstract Field Programmable Gate Array (FPGA) market is growing rapidly with various applications in different industries. There is a new concept evolving in FPGA industry called Dynamic Partial Reconfiguration (DPR) with has a greater exposure in different applications. Partial reconfiguration is ..."
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Abstract Field Programmable Gate Array (FPGA) market is growing rapidly with various applications in different industries. There is a new concept evolving in FPGA industry called Dynamic Partial Reconfiguration (DPR) with has a greater exposure in different applications. Partial reconfiguration
System Level Support for Dynamic Partial Reconfiguration
, 2011
"... In this thesis a generic approach for integrating a dynamically recon-figurable device into a general purpose system interconnected with a high-speed interconnect, is described. The system dynamically installs and executes hardware instances implementing functions to accelerate parts of a particular ..."
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using a secure audio processing application. This is done through acceleration of the audio processing kernel in hardware and subsequently an AES encryption function is configured via dynamic partial reconfiguration. Experimental results with up to 2GB of data show that our solution is up to 12 times
Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration
"... Abstract- In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware servi ..."
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Cited by 1 (1 self)
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Abstract- In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware
Scalable FPGA-based Architecture for DCT Computation Using Dynamic Partial Reconfiguration
"... In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware servicing. Our ..."
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Cited by 11 (2 self)
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In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware servicing. Our
Hardware context switching methodology for dynamically partially reconfigurable systems
- in Proceedings of the National Computer Symposium
, 2007
"... Nowadays, the hardware of field programmable gate arrays (FPGAs) can be reconfigured both dynamically and partially. A dynamically and partially reconfigurable system can share hardware contexts among various hardware tasks. However, such FPGA systems require much memory to save the hardware context ..."
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Cited by 1 (0 self)
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Nowadays, the hardware of field programmable gate arrays (FPGAs) can be reconfigured both dynamically and partially. A dynamically and partially reconfigurable system can share hardware contexts among various hardware tasks. However, such FPGA systems require much memory to save the hardware
On the FPGA Dynamic Partial Reconfiguration Interference on Real-Time Systems
"... Abstract—This work proposes a deterministic hardware and software reconfiguration scheme capable of mitigating interfer-ence on reconfiguration execution time generated by system components performing I/O operations. The scheme decomposes the reconfiguration process into small steps such that it is ..."
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% when real-time threads are performing I/O operations during hardware reconfiguration. Keywords—Dynamic partial reconfiguration, Real-Time, Field-programmable gate arrays (FPGAs), System-level design, HW/SW
Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors
"... Abstract — We introduce a sustainable system design for image processing applications by prototyping a Sobel edge-detection approach suitable for harsh operating environments. The resulting Reconfigurable Adaptive Redundancy System (RARS) is demonstrated on a Xilinx Virtex-4 device with the JTAG por ..."
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Cited by 1 (1 self)
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, dynamic partial reconfiguration is utilized to reduce the bitstream transfer time and thus improve the performance of the GA. This results in an autonomous sustainable approach which supplies useful throughput at a degraded rate even during the repair period.
Performance Enhancement of AES Algorithm Using Dynamic Partial Reconfiguration
"... ABSTRACT: This work reports Partial Reconfiguration (PR) by which FPGA can dynamically reconfigure. The concept of self-reconfiguration is tried to explain under the control of embedded microprocessor like microblaze. Here PR could be useful to reduce area requirements and upsurge systems versatili ..."
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ABSTRACT: This work reports Partial Reconfiguration (PR) by which FPGA can dynamically reconfigure. The concept of self-reconfiguration is tried to explain under the control of embedded microprocessor like microblaze. Here PR could be useful to reduce area requirements and upsurge systems
Results 1 - 10
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15,882
