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Adding a Vector Unit to a Superscalar Processor
, 1999
"... The focus of this paper is on adding a vector unit to a superscalar core, as a way to scale current state of the art superscalar processors. The proposed architecture has a vector register file that shares functional units both with the integer datapath and with the floating point datapath. A key po ..."
Abstract
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Cited by 22 (11 self)
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point in our proposal is the design of a high performance cache interface that delivers high bandwidth to the vector unit at a low cost and low latency. We propose a double-banked cache with alignment circuitry to serve vector accesses and we study two cache hierarchies: one feeds the vector unit from
Scaling Single-Program Performance on Large-Scale Chip Multiprocessors
"... Due to power constraints, computer architects will exploit TLP instead of ILP for future performance gains. Today, 4–8 state-of-the-art cores or 10s of smaller cores can fit on a single die. For the foreseeable future, the number of cores will likely double with each successive processor generation. ..."
Abstract
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necessary. Perhaps the greatest threat to processor utilization will be the overhead incurred waiting on the memory system, especially as on-chip concurrency scales to 100s of threads. In particular, remote cache bank access and off-chip bandwidth contention are likely to be the most significant obstacles
Date Approved
, 2014
"... In recent years, a number of trends have started to emerge, both in micropro-cessor and application characteristics. As per Moore’s law, the number of cores on chip will keep doubling every 18-24 months. International Technology Roadmap for Semiconductors (ITRS) reports that wires will continue to s ..."
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to scale poorly, exacerbating the cost of on-chip communication. Cores will have to navigate an on-chip network to access data that may be scattered across many cache banks. The number of pins on the package, and hence available off-chip bandwidth, will at best increase at sublinear rate and at worst
De-indirection for Flash-based Solid State Drives
, 2013
"... ii iv vTo my parents vi vii Acknowledgements I would first and foremost extend my whole-hearted gratitude to my advisors, An-drea Arpaci-Dusseau and Remzi Arpaci-Dusseau. Andrea and Remzi are the reason that I had the opportunity for this exceptional Ph.D. journey. To this day, I still re-member the ..."
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ii iv vTo my parents vi vii Acknowledgements I would first and foremost extend my whole-hearted gratitude to my advisors, An-drea Arpaci-Dusseau and Remzi Arpaci-Dusseau. Andrea and Remzi are the reason that I had the opportunity for this exceptional Ph.D. journey. To this day, I still re-member the moment when they took me as their student and the joy and hope in my heart. Andrea and Remzi have showed me what systems research is like and how much fun and challenging it can be. Before this journey with them, I had always liked and believed in the beauty of mathematics and theory. My initial interest in systems research happened when I took Remzi’s Advanced Operating Systems
Microsoft Word - FERRIS.doc
"... then in the employ of the American Fur Company CHAPTER I Westward! Ho! It is the sixteenth of the second month A. D. 1830. and I have joined a trapping, trading, hunting expedition to the Rocky Mountains. Why, I scarcely know, for the motives that induced me to this step were of a mixed complexion, ..."
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this, we reached and passed through the village of Franklin, which a pitiless monster was in the act of swallowing up. The river is every year encroaching on the bank that forms the site of the town, and several buildings have already made an aquatic excursion. Others seem preparing to follow. Near
