### Table 1. Minus Log likelihood Digit Training (bits/digit) Testing (bits/digit)

"... In PAGE 3: ...From Table1 , we can see that the likelihood of LNCLT is greater than the one of CLT both in training dataset and testing dataset. This result is consistent with our theoretical analysis in Appendix.... ..."

### Table 1. Minus Log Likelihood Digit Training (bits/digit) Testing (bits/digit) LNCLT CLT LNCLT CLT

"... In PAGE 16: ...From Table1 , we can see that the log likelihood of the LNCLT is larger than that of the CLT for all the ten digits both in training dataset and test dataset. This result shows that the LNCLT approximates the data more ac- curately, which is consistent with our theoretical analysis in the previous sec-... ..."

### Table 1. Minus Log Likelihood Digit Training (bits/digit) Testing (bits/digit) LNCLT CLT LNCLT CLT

"... In PAGE 16: ...From Table1 , we can see that the log likelihood of the LNCLT is larger than that of the CLT for all the ten digits both in training dataset and test dataset. This result shows that the LNCLT approximates the data more ac- curately, which is consistent with our theoretical analysis in the previous sec-... ..."

### Table 3: Quantitative comparison of NST and other divider designs.

1998

"... In PAGE 11: ... 4.2 Quantitative comparison of \mr quot; with other dividers In [8], a detailed comparison of \MROR quot; (Divider 2 in Table3 ) with dividers (3) to (9), listed in Table 3, was presented and it was shown that \MROR quot; has a speedup over all the other divider designs but it has an area disadvantage with regard to architectures which do not require pre- scaling. In this section, we compare the logic implementation of the \mr quot; division presented in section 8 of reference [9]4 with \MROR quot; [8] and then extrapolate the results to the other dividers.... In PAGE 11: ... 4.2 Quantitative comparison of \mr quot; with other dividers In [8], a detailed comparison of \MROR quot; (Divider 2 in Table 3) with dividers (3) to (9), listed in Table3 , was presented and it was shown that \MROR quot; has a speedup over all the other divider designs but it has an area disadvantage with regard to architectures which do not require pre- scaling. In this section, we compare the logic implementation of the \mr quot; division presented in section 8 of reference [9]4 with \MROR quot; [8] and then extrapolate the results to the other dividers.... In PAGE 13: ... Table 3 includes the comparison of the area requirement of \mr quot; with the other dividers ignoring the latches and the area required by the quotient-digit selection logic, which is independent of the word length W , as these are basically the same for all the designs. Excluding the radix 2 implementations (Dividers 7, 8 and 9 in Table3 ), the \mr quot; divider is smaller than all other dividers (with and without pre-scaling). Notably, \mr quot; is smaller than \MROR quot; by W CFA cells and 0:5 W latches.... ..."

Cited by 3

### Table 4: tradeoffs for 4-bit digit serial Carry Select Adder

"... In PAGE 2: ... Although Figure 3 design adds the Mux area to the adder of Figure 2, there is a considerable decrease in the latency. Table4 and Table 5 present the latency, area and speedup of pipelined Carry Select Adder (CSA) with different numbers of stages for addition of 160-bit operands where 8 pipelined 4-bit RCA adders are operated in parallel (2 stages). One stage is added to select the correct sum and carry output from each RCA.... ..."

### Table 2: tradeoffs for 4-bit RCA digit serial adder

"... In PAGE 2: ... Gate counts are used to be completely independent to the technology improvement. Table2 and Table 3 present various tradeoffs for 4-bit adder and 16- bit adder respectively. 3.... ..."

### Table 3: Compression rates (bits per digit) for the single

1998

Cited by 30

### Table 1: Number of bits required for quotient-digit selection functions.

1993

"... In PAGE 5: ... When sum and carry bits are expressed in parenthesis, (s-c), the cor- responding bits are rst assimilated and then used by the speculation function. Since the probability of suc- cess is relatively high and the number of bits signif- icantly smaller than those of Table1 , the approach looks promising. radix 4 8 16 a 2 5 12 # bits ^ ws (s-c) 4-4 5-4 (6-5) # bits ^ ds 0 1 1 prob.... ..."

Cited by 5

### Table 1. Two-bit encoding of BSD digits.

### Table 3. Comparison of digit-serial FIR and bit-parallel FIR Critical Sampling Area-time

1998

"... In PAGE 5: ... Pipeline registers are inserted between multipliers and adders in the same manner as the bit- parallel FIR case. The area and critical path of these two approaches are summarized in Table3 . The tech- nology used is 0.... ..."

Cited by 1