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Design Verification

by Ó T. Brusse-gendre V
"... Design verification is an essential step in the development of any product. Also referred to as qualification testing, design verification ensures that the product as designed is the same as the product as intended. Unfortunately, many design projects do not complete thorough design qualification re ..."
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Design verification is an essential step in the development of any product. Also referred to as qualification testing, design verification ensures that the product as designed is the same as the product as intended. Unfortunately, many design projects do not complete thorough design qualification

Design, Verification

by Paola Inverardi, Henry Muccini, Patrizio Pelliccione
"... Charmy is a framework for designing and validating architectural specifications. In the early stages of the software development process, the Charmy framework assists the software architect in the design and validation phases. To increase its usability in an industrial context, the tool allows the u ..."
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Charmy is a framework for designing and validating architectural specifications. In the early stages of the software development process, the Charmy framework assists the software architect in the design and validation phases. To increase its usability in an industrial context, the tool allows

Design, Verification

by Keith Holman, Jeremy Kuzub, Mohammad Moallemi, Gabriel Wainer
"... We show the design and implementation of a robot controller with a unique locomotion system. We demonstrate that a discrete-event simulation based design provides a cost-effective, flexible [1] , open workflow for modular robotic development. The robot is designed to translate against a vertical sur ..."
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We show the design and implementation of a robot controller with a unique locomotion system. We demonstrate that a discrete-event simulation based design provides a cost-effective, flexible [1] , open workflow for modular robotic development. The robot is designed to translate against a vertical

Design, Verification

by Rohit Gheyi
"... Semantics-preserving model transformations are usually proposed in an ad hoc way because it is difficult to prove that they are sound with respect to a formal semantics. So, simple mistakes lead to incorrect transformations that might, for example, introduce inconsistencies to a model. In order to a ..."
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to avoid that, we propose a set of simple modeling laws (which can be seen as bi-directional transformations) that can be used to safely derive more complex semanticspreserving transformations, such as refactorings which are useful, for example, to introduce design patterns into a model. Our laws

Design; Verification

by Keunhong Lee, Joongi Kim, Sue Moon
"... We present the KENSv2 (KAIST Educational Network System) framework for network protocol implementation. The framework is event-driven to guarantee deterministic behaviour and reproducibility, which in turn delivers ease of debugging and evaluation. Our framework consists of four components: the even ..."
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: specification, paired, and logic tests. The frame-work logs packet transmissions in the PCAP format to allow use of widely available packet analysis tools. Those tools help inspecting logical behaviour of student solutions, such as congestion control. We have designed five step-by-step assignments and evaluated

Design, Verification

by Ufuk Topcu, Richard M. Murray
"... In this paper, we describe a receding horizon scheme that satisfies a class of linear temporal logic specifications suffi-cient to describe a wide range of properties including safety, stability, progress, obligation, response and guarantee. The resulting embedded control software consists of a goal ..."
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In this paper, we describe a receding horizon scheme that satisfies a class of linear temporal logic specifications suffi-cient to describe a wide range of properties including safety, stability, progress, obligation, response and guarantee. The resulting embedded control software consists of a goal gener-ator, a trajectory planner, and a continuous controller. The goal generator essentially reduces the trajectory generation problem to a sequence of smaller problems of short horizon while preserving the desired system-level temporal proper-ties. Subsequently, in each iteration, the trajectory plan-ner solves the corresponding short-horizon problem with the currently observed state as the initial state and generates a feasible trajectory to be implemented by the continuous con-troller. Based on the simulation property, we show that the composition of the goal generator, trajectory planner and continuous controller and the corresponding receding hori-zon scheme guarantee the correctness of the system. To han-dle failures that may occur due to a mismatch between the actual system and its model, we propose a response mech-anism and illustrate, through an example, how the system is capable of responding to certain failures and continues to exhibit a correct behavior.

Computer-Assistant Design Verification

by Er N. Inozemtsev, Dmitry I. Troitsky, Nataly S. Grigorieva, Mark W. Mck Bannatyne
"... Investigation of the quality management problem in design documentation development with the hierarchy analysis method has revealed a conflict of interests between the designer and the standard-compliance verification controller. The proposed IDEF model of design verification procedures helps obtain ..."
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Investigation of the quality management problem in design documentation development with the hierarchy analysis method has revealed a conflict of interests between the designer and the standard-compliance verification controller. The proposed IDEF model of design verification procedures helps

Microprocessor Design Verification

by Warren Hunt, Copyright Warren, A. Hunt - Journal of Automated Reasoning , 1989
"... The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32-bit general purpose, von Neumann processor whose design-level (gate-level) specification has been verified with respect to its instruction-level specification ..."
Abstract - Cited by 60 (3 self) - Add to MetaCart
The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32-bit general purpose, von Neumann processor whose design-level (gate-level) specification has been verified with respect to its instruction

Design Verification for Control Engineering

by Richard J. Boulton, Hanne Gottliebsen, Ruth Hardy, Tom Kelsey, Ursula Martin , 2004
"... We introduce control engineering as a new domain of application for formal methods. We discuss design verification, drawing attention to the role played by diagrammatic evaluation criteria involving numeric plots of a design, such as Nichols and Bode plots. We show that symbolic computation and ..."
Abstract - Cited by 3 (1 self) - Add to MetaCart
We introduce control engineering as a new domain of application for formal methods. We discuss design verification, drawing attention to the role played by diagrammatic evaluation criteria involving numeric plots of a design, such as Nichols and Bode plots. We show that symbolic computation

Incremental Formal Design Verification

by Gitanjali M. Swamy, Robert K. Brayton - in Proc. Intl. Conf. on Computer-Aided Design , 1994
"... Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of its specifications (properties or requirements). If this check fails, language containment returns a subset of `fair' states involved in be ..."
Abstract - Cited by 4 (3 self) - Add to MetaCart
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of its specifications (properties or requirements). If this check fails, language containment returns a subset of `fair' states involved
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