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794
Data Transformations for Eliminating Conflict Misses
- In Proceedings of the SIGPLAN '98 Conference on Programming Language Design and Implementation
, 1998
"... Many cache misses in scientific programs are due to conflicts caused by limited set associativity. We examine two compile-time data-layout transformations for eliminating conflict misses, concentrating on misses occuring on every loop iteration. Inter-variable padding adjusts variable base addresses ..."
Abstract
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Cited by 134 (12 self)
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Many cache misses in scientific programs are due to conflicts caused by limited set associativity. We examine two compile-time data-layout transformations for eliminating conflict misses, concentrating on misses occuring on every loop iteration. Inter-variable padding adjusts variable base
Reducing Conflict Misses in Caches
, 2003
"... Nearly all modern computing systems employ caches to hide the memory latency. Modern processors often employ multiple levels of cache, with one or more levels on the same die as the processor core. As performance demands increase, it becomes increasingly important for an on-die cache structure to pe ..."
Hardware Identification of Cache Conflict Misses
- In Proceedings of the 32nd Annual International Symposium on Microarchitecture
, 1999
"... This paper describes the Miss Classification Table, a simple mechanism that enables the processor or memory controller to identify each cache miss as either a conflict miss or a capacity (non-conflict) miss. The miss classification table works by storing part of the tag of the most recently evicted ..."
Abstract
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Cited by 15 (0 self)
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This paper describes the Miss Classification Table, a simple mechanism that enables the processor or memory controller to identify each cache miss as either a conflict miss or a capacity (non-conflict) miss. The miss classification table works by storing part of the tag of the most recently evicted
Eliminating Conflict Misses for Tiled Codes
"... Tiling is a powerful compiler technique for exploiting data locality in scientific codes. However, previous research has shown conflict misses occurring due to caches with limited associativity can significantly degrade the performance of tiled codes. Two approaches for avoiding conflict misses are ..."
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Tiling is a powerful compiler technique for exploiting data locality in scientific codes. However, previous research has shown conflict misses occurring due to caches with limited associativity can significantly degrade the performance of tiled codes. Two approaches for avoiding conflict misses
Evaluating a model for cache conflict miss prediction
, 2005
"... Cache conflict misses can cause severe degradation in application performance. Previous research has shown that for many scientific applications majority of cache misses are due to conflicts in cache. Although, conflicts in cache are a major concern for application performance it is often difficult ..."
Abstract
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Cited by 7 (1 self)
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Cache conflict misses can cause severe degradation in application performance. Previous research has shown that for many scientific applications majority of cache misses are due to conflicts in cache. Although, conflicts in cache are a major concern for application performance it is often difficult
Near-Optimal Padding for Removing Conflict Misses
- In Languages and Compilers for Parallel Computers
, 2002
"... The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as padding, which is a code transformation targeted to reduce conflict misses. This paper presents a novel ..."
Abstract
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Cited by 9 (3 self)
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The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as padding, which is a code transformation targeted to reduce conflict misses. This paper presents a
Compiler Optimizations for Eliminating Cache Conflict Misses
, 1997
"... Limited set-associativity in hardware caches can cause conflict misses when multiple data items map to the same cache locations. Conflict misses have been found to be a significant source of poor cache performance in scientific programs, particularly within loop nests. We present two compiler transf ..."
Abstract
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Cited by 7 (1 self)
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Limited set-associativity in hardware caches can cause conflict misses when multiple data items map to the same cache locations. Conflict misses have been found to be a significant source of poor cache performance in scientific programs, particularly within loop nests. We present two compiler
Eliminating Conflict Misses for High Performance Architectures
- In Proceedings of the 1998 ACM International Conference on Supercomputing
, 1998
"... Many cache misses in scientific programs are due to conflicts caused by limited set associativity. Two data-layout transformations, inter- and intra-variable padding, can eliminate many conflict misses at compile time. We present GroupPad, an inter-variable padding heuristic to preserve group reuse ..."
Abstract
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Cited by 36 (5 self)
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Many cache misses in scientific programs are due to conflicts caused by limited set associativity. Two data-layout transformations, inter- and intra-variable padding, can eliminate many conflict misses at compile time. We present GroupPad, an inter-variable padding heuristic to preserve group reuse
Avoiding Conflict Misses Dynamically in Large Direct-Mapped Caches
- In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems
, 1994
"... This paper describes a method for improving the performance of a large direct-mapped cache by reducing the number of conflict misses. Our solution consists of two components: an inexpensive hardware device called a Cache Miss Lookaside (CML) buffer that detects conflicts by recording and summarizing ..."
Abstract
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Cited by 108 (4 self)
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This paper describes a method for improving the performance of a large direct-mapped cache by reducing the number of conflict misses. Our solution consists of two components: an inexpensive hardware device called a Cache Miss Lookaside (CML) buffer that detects conflicts by recording
Cache Conscious Data Layout Organization For Conflict Miss
"... Cache misses form a major bottleneck for real-time multimedia applications due to the offchip accesses to the main memory. This results in both a major access bandwidth overhead (and related power consumption) as well as performance penalties. In this paper, we propose a new technique for organiz ..."
Abstract
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Cited by 3 (0 self)
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for organizing data in the main memory for data dominated multimedia applications so as to reduce majority of the conflict cache misses. The focus of this paper is on the formal and heuristic algorithm we use to steer the data layout decisions and the experimental results obtained using a prototype tool
Results 1 - 10
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794
