This paper presents a verification methodology for configurable processor cores. The simulation-based approach uses directed diagnostics and pseudo-random program generators both of which are tailored to specific processor instances. A configurable and extensible test-bench serves as the framework

ii This is dedicated to everyone who has ever helped me. iii ACKNOWLEDGEMENTS I would like to thank my co-advisors Dr. David Whalley and Dr. Gary Tyson for helping me through this process. I acknowledge Antonia Emperato for her support and help during the writing of this thesis.

emerged configurable and extensible processor architectures offer a favorable tradeoff between efficiency and flexibility, and a promising way to minimize certain important metrics (e.g., execution time, code size, etc.) of the embedded processors. This paper addresses the problem of generating

Abstract — Customizable/extensible processors can be tuned to exploit applications of interest in modern platform-based design. However, in most cases they are implemented as extensions of legacy architectures, a policy that poses significant limitations to achieving high performance improvements

In this paper, we demonstrate how to design an optimized processor to achieve fast IP packet forwarding. By developing 2 customized instructions, we show how to achieve one routing lookup with 2 instructions compared with 100+ instructions with standard RISC processor. By using real routing table

This work discusses the Memory Architecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configurable caches) and regular accesses (via pre-fetching stream buffers). By hiding specifics behind a consistent abstract

Abstract approved:

Configurable processors, which allow customization and extension of the base instruction set architecture for a specific application or a domain of applications, are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady

to achieve fast IP packet classification with a configurable processor as a more flexible and future proof alternative to using a hard-wired ASIC. Configurable processors can be tuned by the system designer with new instructions and hardware. To accelerate table lookups and bitmap manipulation, we develop

of a reconfigurable CMP memory system—and to successfully tape out an 8-core CMP chip with only a small group of designers. One person was able to handle processor configuration and hardware generation, support of a complete software tool chain, as well as developing the custom runtime software