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895
Energy-Aware Exploration of Coarse Grained Reconfigurable Processors
"... In recent years Coarse Grained Reconfigurable Architectures (CGRAs) have emerged as a viable option in embedded systems. In this paper we present a power breakdown analysis of such an CGRA. We also present an energy aware exploration for one of the most important, but often neglected parts of proces ..."
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In recent years Coarse Grained Reconfigurable Architectures (CGRAs) have emerged as a viable option in embedded systems. In this paper we present a power breakdown analysis of such an CGRA. We also present an energy aware exploration for one of the most important, but often neglected parts
MORA -an architecture and programming model for a resource efficient coarse grained reconfigurable processor
"... Abstract ..."
Low power coarse-grained reconfigurable instruction set processor
- In 3th Intl. Conf. on Field Programmable Logic and Applications
, 2003
"... Abstract — In this paper, we present a novel coarse-grained reconfigurable processor and study its power consumption. Preliminary results show that the presented coarse-grained processor can achieve on average 2.5x the performance of a RISC processor at an 18 % overhead in energy consumption. I. ..."
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Cited by 6 (0 self)
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Abstract — In this paper, we present a novel coarse-grained reconfigurable processor and study its power consumption. Preliminary results show that the presented coarse-grained processor can achieve on average 2.5x the performance of a RISC processor at an 18 % overhead in energy consumption. I.
A Coarse-Grained Reconfigurable Architecture Supporting Flexible Execution
"... In our research, we have proposed a reconfigurable architecture ’PARS ’ for general purpose. For developing a software assets required as a general purpose processor, the PARS architecture introduces an I-PARS execution model as an ideal execution model for coarse-grained reconfigurable processors. ..."
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In our research, we have proposed a reconfigurable architecture ’PARS ’ for general purpose. For developing a software assets required as a general purpose processor, the PARS architecture introduces an I-PARS execution model as an ideal execution model for coarse-grained reconfigurable processors
2008, ‘Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder’. Journal of Signal Processing Systems
"... Abstract. ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications which demand high-performance, low-power and high-level language programmability. Compared with typical VLIW-based ..."
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Cited by 3 (1 self)
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Abstract. ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications which demand high-performance, low-power and high-level language programmability. Compared with typical VLIW
Coarse-grained Dynamically Reconfigurable Processors
"... Configuration with Self-configured Data Path (CSDP) is a high speed configuration data loading method for Dy-namically Reconfigurable Processors (DRPs). By using a prepared configuration data, a network for computation in DRPs can be used as a configuration data path when the computation is stalled ..."
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Configuration with Self-configured Data Path (CSDP) is a high speed configuration data loading method for Dy-namically Reconfigurable Processors (DRPs). By using a prepared configuration data, a network for computation in DRPs can be used as a configuration data path when the computation is stalled
Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor
"... Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multicontext functionality ..."
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Cited by 1 (1 self)
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Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multicontext
unknown title
"... Abstract – Primary requirements of wireless multimedia handheld computers are high-performance, flexibility, energy-efficiency and low costs. A compromise for these contradicting requirements can be found in a heterogeneous SoC. Besides conventional architectures such a SoC contains domain specific ..."
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coarse grain reconfigurable processors and fine-grain reconfigurable entities. The MONTIUM is a prototype of a novel coarse-grain reconfigurable processor. The SoC template offers a balance between flexibility, efficiency and performance. In this paper the energy and performance characteristics
Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology
"... We evaluate the effect of processor speed, network characteristics, and software overhead on the performance of release-consistent software distributed shared memory. We examine five different protocols for implementing release consistency: eager update, eager invalidate, lazy update, lazy invalidat ..."
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Cited by 467 (43 self)
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invalidate, and a new protocol called lazy hybrid. This lazy hybrid protocol combines the benefits of both lazy update and lazy invalidate. Our simulations indicate that with the processors and networks that are becoming available, coarse-grained applications such as Jacobi and TSP perform well, more or less
The Case for a Single-Chip Multiprocessor
- IEEE Computer
, 1996
"... Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we look for new ways to use their capabilities effectively. This paper shows that in advanced technologies it is possible to ..."
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Cited by 440 (6 self)
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to implement a single-chip multiproces-sor in the same area as a wide issue superscalar processor. We find that for applications with little parallelism the performance of the two microarchitectures is comparable. For applications with large amounts of parallelism at both the fine and coarse grained levels
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