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769
Power-aware clock tree planning
- ISPD'04
, 2004
"... Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability of integrated circuits featuring nanometric technologies. And the power problem is further exacerbated by the increasing ..."
Abstract
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Cited by 13 (0 self)
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, they are subject to a high switching activity. The problem of automatically synthesizing a power efficient clock tree has been addressed recently in a few research contributions. In this paper, we introduce a methodology in which low-power clock trees are obtained through aggressive
Low-power Clock Trees for CPUs
"... Abstract—Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a large parameter space and the increasing impact of process variation make clock network synthesis particularly c ..."
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Cited by 7 (5 self)
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challenging. In this work, we develop new modeling techniques and algorithms, as well as a methodology, for clock power optimization subject to tight skew constraints in the presence of process variations. Key contributions include a new time-budgeting step for clock-tree tuning, accurate optimizations
Clock Tree Generation Beating the clock?
"... Abstract — This paper describes why the distribution of the clock in modern systems is so important for the overall performance of the design. It also examines some of the method that modern EDA tools uses for the design of clock distribution networks. As the requirements on performance, low power a ..."
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Abstract — This paper describes why the distribution of the clock in modern systems is so important for the overall performance of the design. It also examines some of the method that modern EDA tools uses for the design of clock distribution networks. As the requirements on performance, low power
Process Variation Robust Clock Tree Routing
, 2005
"... As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based approach to perform simultaneous non-zero clock skew scheduling and clock tree routing, taking into consideration the effect ..."
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As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based approach to perform simultaneous non-zero clock skew scheduling and clock tree routing, taking into consideration
Activity-sensitive clock tree construction for low power
- in Proc. Int. Symp. on Low Power Electronics and Design
, 2002
"... This paper presents an activity-sensitive clock tree construction technique for low power design of VLSI clock networks. We introduce the term of node difference based on module activity information, and show its relationship with the power consumption. A binary clock tree is built using the node di ..."
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Cited by 10 (0 self)
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This paper presents an activity-sensitive clock tree construction technique for low power design of VLSI clock networks. We introduce the term of node difference based on module activity information, and show its relationship with the power consumption. A binary clock tree is built using the node
OCV-Aware Top-Level Clock Tree Optimization
"... The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock gating cells, multiplexers and dividers) in order to achieve aggressive clock gating and required performance across a wide range of operating modes and conditions. As a result, clock tree structures ha ..."
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The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock gating cells, multiplexers and dividers) in order to achieve aggressive clock gating and required performance across a wide range of operating modes and conditions. As a result, clock tree structures
Transmission line design of clock trees
- in Proc. Int. Conf. on Computer Aided Design
, 2002
"... We investigate appropriate regimes for transmission line propagation of signals on digital integrated circuits. We start from exact solutions to the transmission line equations proposed by Davis and Meindl. We make appropriate modifications due to finite rise time. They affect the delay calculation ..."
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Cited by 5 (0 self)
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insertion in the presence of transmission lines. The resulting configurations are suitable for the development of an improved clock design discipline. 1.
Clock Tree Synthesis with Data-Path Sensitivity Matching
"... Abstract — This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit variations and most papers on data-path circuit optimization dis-regard clock tree variation, we consider bo ..."
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Abstract — This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit variations and most papers on data-path circuit optimization dis-regard clock tree variation, we consider
Schedule-Clock-Tree Routing for Semi-Synchronous Circuits
, 1999
"... this paper we propose a clock-tree routin algorithm that realizes a given clock-scheduleusin the Elmore-delay model. Followin the deferred-merge-embeddin (DME) framework the algorithm genm,697 a topology of the clock-treean simultan67,R] determin, the location an sizes ofin termediate bu#ers. The ex ..."
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Cited by 4 (1 self)
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this paper we propose a clock-tree routin algorithm that realizes a given clock-scheduleusin the Elmore-delay model. Followin the deferred-merge-embeddin (DME) framework the algorithm genm,697 a topology of the clock-treean simultan67,R] determin, the location an sizes ofin termediate bu
Results 1 - 10
of
769
