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Satisfiability Models and Algorithms for Circuit Delay

by Luís Guerra E Silva, João P. Marques Silva, Luís Miguel Silveira, Karem A. Sakallah - Computation,” in Workshop on Timing Issues in the Specification and Synthesis of Digital Systems , 1997
"... The existence of false paths represents a significant and computationally complex problem in computing the delay of combinational and sequential circuits. Existing research work on circuit delay computation by taking false paths into account has focused on three main areas: gate delay models, path s ..."
Abstract - Cited by 8 (4 self) - Add to MetaCart
The existence of false paths represents a significant and computationally complex problem in computing the delay of combinational and sequential circuits. Existing research work on circuit delay computation by taking false paths into account has focused on three main areas: gate delay models, path

Analysis of APS Readout Circuit Delay

by Khaled Salama, Abbas El Gamal
"... The paper provides a complete analysis of the APS pixel and column circuit delay. Contrary to common belief, we show that shorter settling times can be achieved by reducing the bias current and hence reducing energy consumption. We then investigate the effect of non-idealities on the readout operati ..."
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The paper provides a complete analysis of the APS pixel and column circuit delay. Contrary to common belief, we show that shorter settling times can be achieved by reducing the bias current and hence reducing energy consumption. We then investigate the effect of non-idealities on the readout

On the Average Case Circuit Delay of Disjunction

by Beate Bollig, Martin Hühne, Stefan Pölt, Petr Savicky , 1994
"... For circuits the expected delay is a suitable measure for the average case time complexity. In this paper, new upper and lower bounds on the expected delay of circuits for disjunction and conjunction are derived. The circuits presented yield asymptotically optimal expected delay for a wide class of ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
For circuits the expected delay is a suitable measure for the average case time complexity. In this paper, new upper and lower bounds on the expected delay of circuits for disjunction and conjunction are derived. The circuits presented yield asymptotically optimal expected delay for a wide class

Satisfiability Models and Algorithms for Circuit Delay Computation

by Luís Guerra, E Silva, João Marques-silva, L. Miguel Silveira, Karem A. Sakallah
"... The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of combinational and sequential circuits. In this article we conduct a comprehensive study of modeling circuit delay computation, accounting for false paths, as a sequence of ..."
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The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of combinational and sequential circuits. In this article we conduct a comprehensive study of modeling circuit delay computation, accounting for false paths, as a sequence

Computation and refinement of statistical bounds on circuit delay

by Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma Vrudhula - Proc. 2003 Design Automation Conference , 2003
"... The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies ..."
Abstract - Cited by 35 (2 self) - Add to MetaCart
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies

Delayed internet routing convergence

by Craig Labovitz, Abha Ahuja, Abhijit Bose, Farnam Jahanian - ACM SIGCOMM Computer Communication Review , 2000
"... Abstract—This paper examines the latency in Internet path failure, failover, and repair due to the convergence properties of interdomain routing. Unlike circuit-switched paths which exhibit failover on the order of milliseconds, our experimental mea-surements show that interdomain routers in the pac ..."
Abstract - Cited by 408 (5 self) - Add to MetaCart
Abstract—This paper examines the latency in Internet path failure, failover, and repair due to the convergence properties of interdomain routing. Unlike circuit-switched paths which exhibit failover on the order of milliseconds, our experimental mea-surements show that interdomain routers

A generalized processor sharing approach to flow control in integrated services networks: The single-node case

by Abhay K. Parekh, Robert G. Gallager - IEEE/ACM TRANSACTIONS ON NETWORKING , 1993
"... The problem of allocating network resources to the users of an integrated services network is investigated in the context of rate-based flow control. The network is assumed to be a virtual circuit, connection-based packet network. We show that the use of Generalized processor Sharing (GPS), when co ..."
Abstract - Cited by 2010 (5 self) - Add to MetaCart
The problem of allocating network resources to the users of an integrated services network is investigated in the context of rate-based flow control. The network is assumed to be a virtual circuit, connection-based packet network. We show that the use of Generalized processor Sharing (GPS), when

A theory of timed automata

by Rajeev Alur , 1999
"... Model checking is emerging as a practical tool for automated debugging of complex reactive systems such as embedded controllers and network protocols (see [23] for a survey). Traditional techniques for model checking do not admit an explicit modeling of time, and are thus, unsuitable for analysis of ..."
Abstract - Cited by 2651 (32 self) - Add to MetaCart
of real-time systems whose correctness depends on relative magnitudes of different delays. Consequently, timed automata [7] were introduced as a formal notation to model the behavior of real-time systems. Its definition provides a simple way to annotate state-transition graphs with timing constraints

Sequential Circuit Delay Optimization Using Global Path Delays

by Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler - In 30th ACM/IEEE Design Automation Conference , 1993
"... ABSTRACT: We propose a novel sequential delay op-timization technique based on network flow methods that simultaneously exploits delays on all paths in the circuit. We view the sequential circuit as an intercon-nection of path segments with pre-specified delays. Path segments are bounded by flip-flo ..."
Abstract - Cited by 10 (0 self) - Add to MetaCart
ABSTRACT: We propose a novel sequential delay op-timization technique based on network flow methods that simultaneously exploits delays on all paths in the circuit. We view the sequential circuit as an intercon-nection of path segments with pre-specified delays. Path segments are bounded by flip

21.3 Computation and Refinement of Statistical Bounds on Circuit Delay

by Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma Vrudhula
"... The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies ..."
Abstract - Add to MetaCart
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies
Results 1 - 10 of 5,645