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331
Cache Interference Phenomena
- In Proceedings of the Sigmetrics Conference on Measurement and Modeling of Computer Systems
, 1994
"... The impact of cache interferences on program performance (particularly numerical codes, which heavily use the memory hierarchy) remains unknown. The general knowledge is that cache interferences are highly irregular, in terms of occurrence and intensity. In this paper, the different types of cache i ..."
Abstract
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Cited by 84 (6 self)
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The impact of cache interferences on program performance (particularly numerical codes, which heavily use the memory hierarchy) remains unknown. The general knowledge is that cache interferences are highly irregular, in terms of occurrence and intensity. In this paper, the different types of cache
Revisiting the Cache Interference Costs of Context Switching
"... The high cost of context switching is one reason that operating system performance is not keeping pace with hardware improvements. Besides the cost of saving and restoring registers, another component of context switch cost is the cache interference between multiple processes sharing the same cache. ..."
Abstract
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Cited by 3 (0 self)
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The high cost of context switching is one reason that operating system performance is not keeping pace with hardware improvements. Besides the cost of saving and restoring registers, another component of context switch cost is the cache interference between multiple processes sharing the same cache
The Cache Performance and Optimizations of Blocked Algorithms
- In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
, 1991
"... Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchies. Instead of operating on entire rows or columns of an array, blocked algorithms operate on submatrices or blocks, so that data loaded into the faster levels of the memory hierarchy are reused. This ..."
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Cited by 574 (5 self)
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. This paper presents cache performance data for blocked programs and evaluates several optimizations to improve this performance. The data is obtained by a theoretical model of data conflicts in the cache, which has been validated by large amounts of simulation. We show that the degree of cache interference
Impact of Cache Interferences on Usual Numerical Dense Loop Nests
- Proceedings of the IEEE
, 1993
"... In numerical codes, the regular interleaved accesses that occur within do-loop nests induce cache interference phenomena that can severely degrade program performance. Cache interferences can significantly increase the volume of memory traffic and the amount of communication in uniprocessors and mul ..."
Abstract
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Cited by 11 (4 self)
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In numerical codes, the regular interleaved accesses that occur within do-loop nests induce cache interference phenomena that can severely degrade program performance. Cache interferences can significantly increase the volume of memory traffic and the amount of communication in uniprocessors
Characterization and Dynamic Mitigation of Intra-Application Cache Interference
"... Abstract—Given the emerging dominance of CMPs, an important research problem concerns application memory performance in the face of deep memory hierarchies, where one or more caches are shared by several cores. In current systems, many factors can cause interference in the shared last-level cache (L ..."
Abstract
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Cited by 13 (2 self)
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Abstract—Given the emerging dominance of CMPs, an important research problem concerns application memory performance in the face of deep memory hierarchies, where one or more caches are shared by several cores. In current systems, many factors can cause interference in the shared last-level cache
A Tile Selection Algorithm for Data Locality and Cache Interference
- In 1999 ACM International Conference on Supercomputing
, 1999
"... Loop tiling is a well-known compiler transformation that increases data locality, exposes parallelism and reduces synchronization costs. Tiling increases the amount of data reuse that can be exploited by reordering the loop iterations so that accesses to the same data are closer together in time. Ho ..."
Abstract
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Cited by 34 (2 self)
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. However, tiled loops often suer from cache interference in the direct-mapped or low-associativity caches typically found in state-of-the-art microprocessors. A solution to this problem is to choose a tile size that does not exhibit self interference. In this paper, we propose a new tile selection
Reduction of Cache Interference Misses through Selective Bit-permutation Mapping
, 1994
"... Cache miss rates have a large and increasing impact on overall performance. In this report, we address the problem of cache interference in regular numerical programs dominated by strided memory access patterns. In our scheme, the interfering strides in each region of memory may be annotated by the ..."
Abstract
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Cited by 4 (0 self)
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Cache miss rates have a large and increasing impact on overall performance. In this report, we address the problem of cache interference in regular numerical programs dominated by strided memory access patterns. In our scheme, the interfering strides in each region of memory may be annotated
Understanding the Impact of Inter-Thread Cache Interference on ILP in Modern SMT Processors
- JOURNAL OF INSTRUCTION-LEVEL PARALLELISM
, 2005
"... Simultaneous Multithreading (SMT) has emerged as an effective method of increasing utilization of resources in modern super-scalar processors. SMT processors increase instruction-level parallelism (ILP) and resource utilization by simultaneously executing instructions from multiple independent threa ..."
Abstract
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Cited by 11 (2 self)
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. This paper explores the design of a novel fine-grained hardware cache monitoring system in an SMT-based processor that enables improved operating system scheduling and recaptures parallelism by mitigating interference.
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems
- In CASES ’07: Proceedings of the 2007 international conference on Compilers, architecture, and
, 2007
"... We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to provide the required memory bandwidth. However, caches introduce two important problems for embedded systems. Cache outcom ..."
Abstract
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Cited by 7 (0 self)
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We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to provide the required memory bandwidth. However, caches introduce two important problems for embedded systems. Cache
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331
