Results 1 - 10 of 214

EFFICIENT BIST SCHEMES FOR RNS DATAPATHS

by D. G. Nikolos, H. T Vergos, C. Efstathiou
"... It has recently been shown that accumulators can be used elf-ciently for test pattem generation as well as for test response com-paction. In this paper we present a BIST scheme for accumula-tors where the accumulator is simultaneously used as a test pattern generator and a response compactor during ..."
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It has recently been shown that accumulators can be used elf-ciently for test pattem generation as well as for test response com-paction. In this paper we present a BIST scheme for accumula-tors where the accumulator is simultaneously used as a test pattern generator and a response compactor during

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs

by In Datapaths, Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, V. H. Champac, M. Lubaszewski , 2000
"... Abstract. In this paper an effective Built-In Self-Test (BIST) scheme for the shifter-accumulator pair (accumu-lation performed either by an adder or an ALU) which appears very often in embedded processor, microprocessor or DSP datapaths is introduced. The BIST scheme provides very high fault covera ..."
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Abstract. In this paper an effective Built-In Self-Test (BIST) scheme for the shifter-accumulator pair (accumu-lation performed either by an adder or an ALU) which appears very often in embedded processor, microprocessor or DSP datapaths is introduced. The BIST scheme provides very high fault

Pattern Generation for a Deterministic BIST Scheme

by Sybille Hellebrand , Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich , 1995
"... Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be su ..."
Abstract - Cited by 38 (8 self) - Add to MetaCart
be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set

An Efficient BIST scheme for High-Speed Adders

by D. G. Nikolos, D. Nikolos, H. T. Vergos, C. Efstathiou
"... In this paper we present a new pseudorandom BIST scheme for high-speed adders. Under this scheme an adder is simultaneously used as a test pattern generator and as a response compactor during its own testing. The main advantages of the proposed scheme, compared to prior methods, are minimal performa ..."
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In this paper we present a new pseudorandom BIST scheme for high-speed adders. Under this scheme an adder is simultaneously used as a test pattern generator and as a response compactor during its own testing. The main advantages of the proposed scheme, compared to prior methods, are minimal

An Efficient BIST Scheme for Non-Restoring Array Dividers

by H. T. Vergos
"... A new effective built-in self-test (BIST) scheme for non-restoring array dividers (NADs) is proposed, that offers more than 99 % cell fault coverage in all NADs of practi-cal use. Moreover, it can be implemented in small hardware and can apply all its test vectors within 128 clock cycles. A version ..."
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A new effective built-in self-test (BIST) scheme for non-restoring array dividers (NADs) is proposed, that offers more than 99 % cell fault coverage in all NADs of practi-cal use. Moreover, it can be implemented in small hardware and can apply all its test vectors within 128 clock cycles. A version

MCBIST: A New On-Line BIST Scheme

by Mohammad Alisafaee, Pejman Lotfikamran, Saeed Shamshiri, Hadi Esmaeilzadeh, Ardavan Pedram, Zainalabedin Navabi
"... ABSTRACT Built-In-Self-Test (BIST) is an efficient and practical technique for testing VLSI circuits and systems. Among the different BIST techniques, the Comparative Concurrent BIST (CBIST) has many advantages since it can provide on-line and off-line testing with the same hardware. However, in CBI ..."
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, in CBIST when the width of the circuit lines increases, on-line testing becomes inefficient. The problem is that finding a match between input data and test sequence has a low chance when the input line width increases. In this paper, we propose MCBIST (Multi CBIST) a new on-line BIST scheme that addresses

Pattern Generation for a Deterministic BIST Scheme

by Sybille Hellebr, Birgit Reeb, Steffen Tarnick, Hans-joachim Wunderlich
"... Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be su ..."
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be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths

by unknown authors
"... Effective Built-In Self-Test (BIST) schemes using deterministic sequences generated by small counters have been proposed in the past for the common multiplier/accumulator pair. In this paper we show how near complete testability can be achieved with a regular counter-generated deterministic test set ..."
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Effective Built-In Self-Test (BIST) schemes using deterministic sequences generated by small counters have been proposed in the past for the common multiplier/accumulator pair. In this paper we show how near complete testability can be achieved with a regular counter-generated deterministic test

Low Power Test Pattern Generation in BIST Schemes

by Yasodharan S, Swamynathan S M
"... ABSTRACT – — BIST is a viable approach to test today's digital systems. During self-test, the switching activity of the Circuit Under Test (CUT) is significantly increased compared to normal operation and leads to an increased power consumption which often exceeds specified limits. The propose ..."
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method is flexible to both the test-per-scan schemes and the test-per-clock. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces

A BIST Scheme for On-chip ADC and DAC Testing

by Jiun-lang Huang, Chee-kian Ong, Kwang-ting Cheng - In Proc. Design, Automation and Test in Europe , 2000
"... In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation—5 % LSB (least significant bit) test ..."
Abstract - Cited by 13 (4 self) - Add to MetaCart
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation—5 % LSB (least significant bit
Results 1 - 10 of 214