For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined global interconnects. In this paper we present an architecture-level synthesis solution to support automatic pipelining

The past and, almost, the current scenario in (mobile) communication net-works is characterized by multiple networking technologies deployed inde-pendently and targetting different services, data rates, and users. Coopera-tion between these networks is still (almost) impossible, and when possible it does not happen in a plug and play way. On the way to next generation net-works, solutions providing support for roaming between cellular and Wi-Fi networks are already available. Nevertheless, the success of future commu-nication networks mostly depends on the full integration of these multiple networks, and new solutions need to be specified. Furthermore, in future net-works new communication paradigms will come up: technology embedded in the user surrounding environment and users owning small moving net-works (e.g., Personal Area Networks), instead of multiple terminals working independently, as it happens today. In this context, autoconfiguration and self-management become crucial requirements. In the past, multiple auto-

Abstract — This paper presents an automatic interconnection rectification (AIR) technique to correct the misplaced interconnection occurred in the integration of a SoC design automatically. The experimental results show that the AIR can correct the misplaced interconnection and therefore

For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined global interconnects. In this paper we present an architecture-level synthesis solution to support automatic pipelining

For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined global interconnects. In this paper we present an architecture-level synthesis solution to support automatic pipelining

[17] K. L. Shepard and V. Narayanan, “Noise in deep submicron digital design,”

We describe a system called Polylith that helps programmers prepare and interconnect mixed-language software components for execution in heterogeneous environments. Polylith's principal benefit is that programmers are free to implement functional requirements separately from their treatment

We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open-via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect

features of the design may still be required, the component-based constraints can be quickly determined and the corresponding file quickly generated by this process. All required design information is gathered from files already used in the interconnect test generation process. Since the pin

Interlinking text documents with Linked Open Data enables the Web of Data to be used as background knowledge within document-oriented applications such as search and faceted browsing. As a step towards interconnecting the Web of Documents with the Web of Data, we developed DBpedia Spotlight, a