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485
At-speed testing made easy At-speed testing made easy
, 2004
"... Today's chip designs are getting smaller and bigger. Feature sizes are moving into nanometer geometries, and gate counts are pushing towards the 100M gate mark. Semiconductor companies creating these nanometer designs are struggling with many issues that result from this shrinking yet increasin ..."
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, like resistive vias and bridges, exhibit defective timing behavior, and therefore, are effectively caught by conducting testing at system speeds. In fact, a leading ASIC vendor documented that their DPM rates were reduced by 30 to 70 percent by adding at-speed testing to their traditional stuck-at
At-speed Testing of SOC ICs
"... This paper discusses the aspects and associated requirements of design and implementation of at-speed scan testing. It also demonstrates some important vector generation and implementation procedures based on a real design. An innovative method of scan pattern timing creation based on the results fr ..."
Abstract
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Cited by 3 (0 self)
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This paper discusses the aspects and associated requirements of design and implementation of at-speed scan testing. It also demonstrates some important vector generation and implementation procedures based on a real design. An innovative method of scan pattern timing creation based on the results
Self-Test Methodology for AtSpeed Test of Crosstalk
- in Chip Interconnects,” in Proc. Design Automation Conf. (DAC’00
, 2000
"... The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that we have developed to enable on-chip at-speed testing of crosstalk defects in System-on-Chip interconnects. The self-test ..."
Abstract
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Cited by 21 (7 self)
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The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that we have developed to enable on-chip at-speed testing of crosstalk defects in System-on-Chip interconnects. The self-test
RTL Analysis and Modifications for Improving At-speed Test
"... Abstract—At-speed testing is increasingly important at recent technology nodes due to growing uncertainty in chip manufacturing. However, at-speed fault coverage and test-efficacy suffer when tests are not robust. Since Automatic Test Pattern Generation (ATPG) is typically performed at late design s ..."
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Abstract—At-speed testing is increasingly important at recent technology nodes due to growing uncertainty in chip manufacturing. However, at-speed fault coverage and test-efficacy suffer when tests are not robust. Since Automatic Test Pattern Generation (ATPG) is typically performed at late design
Programmable Logic BIST for At-speed Test
"... In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing fa ..."
Abstract
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Cited by 1 (0 self)
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In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing
1Statistical Path Selection for At-Speed Test
"... Abstract — Process variations make at-speed testing sig-nificantly more difficult. They cause subtle delay changes that are distributed in contrast to the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process sp ..."
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Cited by 4 (1 self)
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Abstract — Process variations make at-speed testing sig-nificantly more difficult. They cause subtle delay changes that are distributed in contrast to the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process
Statistical Path Selection for At-Speed Test
"... Abstract — Process variations make at-speed testing signifi-cantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process space ..."
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Abstract — Process variations make at-speed testing signifi-cantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process
Statistical Path Selection for At-Speed Test
"... Abstract — Process variations make at-speed testing signifi-cantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process space ..."
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Abstract — Process variations make at-speed testing signifi-cantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process
Improving the proportion of At-Speed Tests in Scan BIST +
"... A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i.e ..."
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A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i
1Optimal Margin Computation for At-Speed Test
"... Abstract — In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly higher speed than the target frequency required in the field. The additional performance required on the tester is cal ..."
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Abstract — In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly higher speed than the target frequency required in the field. The additional performance required on the tester
Results 1 - 10
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485
