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Abstract Deterministic Logic BIST for Transition Fault Testing 1

by Valentin Gherman, Hans-joachim Wunderlich
"... BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLB ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need

Deterministic BIST for RNS Adders

by Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
"... Abstract—Modulo 2n ÿ 1 adders as fast as n-bit 2’s complement adders have been recently proposed in the open literature. This makes a Residue Number System (RNS) adder with channels based on the moduli 2n, 2n ÿ 1, and any other of the form 2k ÿ 1, with k < n, faster than RNS adders based on other ..."
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fault coverage and an attractive combination of test time and implementation area compared to ROM and FSM-based deterministic BIST or LFSR-based pseudorandom BIST. Index Terms—Residue Number System, Built-In Self-Test, deterministic and pseudorandom tests, formal test sets. æ

Application of Deterministic Logic BIST on Industrial Circuits

by Gundolf Kiefer, Harald Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich - In Proceedings IEEE International Test Conference (ITC , 2000
"... We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-1 ..."
Abstract - Cited by 11 (2 self) - Add to MetaCart
We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5

Efficient Pattern Mapping for Deterministic Logic BIST

by Hans-joachim Wunderlich - In Int’l Test Conf , 2004
"... Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis ..."
Abstract - Cited by 8 (3 self) - Add to MetaCart
Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST

Combining deterministic logic bist with test point insertion

by Harald Vranken, Florian Meister, Hans-joachim Wunderlich - In Proceedings European Test Workshop , 2002
"... This paper presents a logic BIST approach which combines deterministic logic BIST with test point insertion. Test points are inserted to obtain a first testability improvement, and next a deterministic pattern generator is added to increase the fault efficiency up to 100%. The silicon cell area for ..."
Abstract - Cited by 4 (1 self) - Add to MetaCart
This paper presents a logic BIST approach which combines deterministic logic BIST with test point insertion. Test points are inserted to obtain a first testability improvement, and next a deterministic pattern generator is added to increase the fault efficiency up to 100%. The silicon cell area

Application of Deterministic Logic BIST on Industrial Circuits

by Gundolf Kiefer Harald, Harald Vranken - In Proceedings IEEE International Test Conference (ITC , 2000
"... We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-1 ..."
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We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5

c ○ 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Application of Deterministic Logic BIST on Industrial Circuits

by Gundolf Kiefer, Hans-joachim Wunderlich, P. Prinetto , 2000
"... Abstract. We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost fo ..."
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Abstract. We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs

by In Datapaths, Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, V. H. Champac, M. Lubaszewski , 2000
"... Abstract. In this paper an effective Built-In Self-Test (BIST) scheme for the shifter-accumulator pair (accumu-lation performed either by an adder or an ALU) which appears very often in embedded processor, microprocessor or DSP datapaths is introduced. The BIST scheme provides very high fault covera ..."
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Abstract. In this paper an effective Built-In Self-Test (BIST) scheme for the shifter-accumulator pair (accumu-lation performed either by an adder or an ALU) which appears very often in embedded processor, microprocessor or DSP datapaths is introduced. The BIST scheme provides very high fault

BIST-Based Test and Diagnosis of FPGA Logic Blocks

by Miron Abramovici, Charles E. Stroud, Senior Member - IEEE Trans. on VLSI Systems , 2001
"... Abstract—We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not i ..."
Abstract - Cited by 42 (17 self) - Add to MetaCart
Abstract—We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does

A New BIST Scheme with Encoding Logic to Achieve Complete Fault Coverage

by Ling Zhang, Junjin Mei, Guan-zhong Wang, Tonghan Li
"... Abstract—Built-in Self Test(BIST)has been proved as one of the effective design for testability techniques, where on-chip test architectures are designed to test the digital circuits themselves. To reduce test application time and improve fault coverage, A deterministic Built-in Self Test(BIST) tech ..."
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Abstract—Built-in Self Test(BIST)has been proved as one of the effective design for testability techniques, where on-chip test architectures are designed to test the digital circuits themselves. To reduce test application time and improve fault coverage, A deterministic Built-in Self Test(BIST
Results 1 - 10 of 661