of the topology and branch lengths, only a few iterations are sufficient to reach an optimum. We used extensive and realistic computer simulations to show that the topological accuracy of this new method is at least as high as that of the existing maximum-likelihood programs and much higher than the performance

Abstract A fast and accurate simulation method for high-speed clock trees with buffer insertions is proposed in this paper, where transmission line model is used in all branches of clock trees rather than only in main path. The proposed method is based on two-moment matching technique and can

This paper introduces a simple and hardware efficient clock recovery method for high speed serial links and compares its performance with conventional techniques. Conventional methods are conceptually complex and difficult to realize since they rely on data transitions to recover the clock

This paper presents a fast wavelet collocation method (FWCM) for high- speed circuit simulation. The FWCM has the following properties: (1) It works in the time domain, so that the circuit nonlinearity can be handled, and the accuracy of the result can be well controlled, unlike the method working

We survey our recent work in the analysis and design of interconnect topologies for high-speed VLSI. Results include: a new, fast distributed RLC analysis method based on a two-pole approximation; an A-tree formulation for performance-driven interconnect; an optimal wiresizing algorithm; and new

y y choi @ ee. tamu.edu, franc0 @ ee. tamu.edu A DAC architecture based on the current steering method is presented. The proposed architecture exploits the oversampling and uses a MASH like configuration. The DAC requires to use two current steering 5-bit D/A converters whose current references

Abstract—As one of the most challenging problems of the next-generation high-speed networks, quality-of- service routing (QoSR) with multiple (k) constraints is an NP-complete problem. In this paper, we propose a multi-constrained energy functionbased precomputation algorithm, MEFPA. It cares each

Abstract. This paper presents a design for testability (DFT) technique for testing high-speed circuits with a low-speed test mode clock. With this technique, the test mode clock frequency can be reduced with virtually no lower limit. Even with the reduced speed requirement on the automatic test

This paper describes a finite state machine approach for string matching within high-speed network intrusion detection systems. This method uses a standard table based finite state machine implementation, but this is preceded by a preliminary stage that compresses multi-byte network input data

Abstract— — High-speed input/outputs (I/O) are in demand due to advances in integrated circuits (ICs), which made it possible to obtain multi gigahertz clock speeds. However, as very large scale integration (VLSI) technology scales down, the pin bandwidth does not scale accordingly. Some factors