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125
UsefulSkew Clock Routing With Gate Sizing for Low Power Design
"... Instead of zeroskew or assuming a xed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skewmay allow a larger timing budget for gate sizing. We construct a usefulskew tree (UST) such that the total clock and logic power(measured as a cost ..."
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Instead of zeroskew or assuming a xed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skewmay allow a larger timing budget for gate sizing. We construct a usefulskew tree (UST) such that the total clock and logic power(measured as a cost
Gated Clock Routing for Low Power
 Video Data Mangement and Information Retrieval
, 2004
"... This paper presents a zeroskew gated clock routing technique for VLSI circuits. Gated clock trees include masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce the ..."
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This paper presents a zeroskew gated clock routing technique for VLSI circuits. Gated clock trees include masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce
ProcessVariation Robust and LowPower ZeroSkew Buffered ClockTree Synthesis Using Projected ScanLine Sampling
"... Processvariation induced skew has become one of the major contributors to the clockskew in advanced technologies. Since processvariation induced skew is roughly proportional to clockdelay, it is preferable to design zeroskew clocktrees and have minimum clockdelay to reduce both unintentional ..."
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also utilize usefulskew and boundedskew constraints to allow more aggrressive optimization. Extensive experimental results show that for an industrial clocktree with 3101 sink nodes, our algorithm achieves up to 45X clockdelay improvement and up to 23% power reduction compared with its initial
Clock gating for low power circuit design by Merge and split methods
"... ABSTRACT In present VLSI technology energy dissipation is an important factor to be considered among other factors like area, speed and performance in portable devices. The size reduction and complexity of portable devices have resulted in large amount of power dissipation in the devices. As a resu ..."
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result low power designs have become inevitable part of today's devices. In this paper low power dissipation is achieved by using clock gating technique. It reduces the dynamic power dissipation by controlling the clock whenever it is not in use. Merge and Split clock gated concepts were applied
Power Reduction Through Clock Gating by Symbolic Manipulation.
 Proc. IFIP Int. Workshop on Logic and Architecture Synthesis
, 1996
"... A method to reduce power dissipation by automatically synthesizing gatedclocks in synchronous static CMOS circuits is presented. This synthesis is performedon the gate level description of the circuit. The boolean behavior of the inputs of the flipflops is determined by examining the network. Th ..."
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Cited by 11 (0 self)
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overhead (less than 8%). Testability of the resulting design is taken care of. Keywords Integrated digital circuit design, lowpower design 1 INTRODUCTION Due to the continuously decreasing feature sizes and the increasing clock frequencies on integrated digital circuits, power dissipation is growing
Low Power Network Processor Design Using Clock Gating
"... Abstract — Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate multiprocessing and multithreading to achieve maximum parallel processing capabilities. We observed that under low incomin ..."
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, and gate off the clock network of unused PEs when a subset of PEs is enough to handle the network traffic. To accommodate different applications and network parameters (i.e. packet size, arrival rate), the thresholds of turning on/off PEs will be dynamically tuned onthefly. We show that our technique
PIII8 ProcessVariation Robust and LowPower ZeroSkew Buffered ClockTree Synthesis Using Projected ScanLine Sampling*
"... jltsaiocae. wisc. edu Abstract Zeroskew clocktree.with minimum clockdelay is preferable due to its low unintentional and processvariation induced skews. We propose a zeroskew buffered clocktree synthesis flow and a novel algorithm that enables clocktree optimization throughout the full zer ..."
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zeroskew designspace by considering simultaneous bufferinsertion, buffersizing, and wiresizing. For an industrial clocktree with 3101 sink nodes, our algorithm,achieves up to 45X clockdelay improvement and up to 23 % power reduction compared with its initial routing. 1.
and register placement aware gated clock network design
 in Proc. ISPD, 2008
"... Clock gating is one of the most effective techniques to reduce clock network power dissipation. Although it has already been studied considerably, most of the previous works are restricted to either logic level or clock routing stage. Due to the restriction, clock gating often meets the trouble of w ..."
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Cited by 6 (0 self)
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topology construction and zero skew clock routing to further reduce the power and the clock skew. Last, the gated clock network is fed back to the placer for incremental placement. Experimental results on ISCAS89 benchmarks demonstrate that our method outperforms previous algorithm of activity aware
www.mdpi.com/journal/jlpea/ Low Power Clock Network Design
, 2011
"... Abstract: Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variat ..."
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Cited by 1 (1 self)
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) variations and load imbalances. A target skew between sequentiallyadjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in treebased clock distribution networks, however, are not efficient in coping
BTIGater: An AgingResilient Clock Gating Methodology
"... (N/PBTI) have become one of the most important reliability issues in modern semiconductor technology. N/PBTIinduced degradation depends heavily on workload, which causes imbalanced degradation and additional clock skew for clock distribution networks with clock gating features. In this work, we fi ..."
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first analyze the effects of N/PBTI on clock paths with different clock gating use cases. Then crosslayer solutions are proposed to reduce N/PBTIinduced clock skew. Two Integrated Clock Gating (ICG) cell circuits are proposed to alternate clock idle state between logic high and logic low for each
Results 1  10
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125