Results 1 - 10 of 28

UltraSPARC TM-I Emulation

by James Gateley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, Tim Goldsbury, Dale Greenley, Raju Joshi, Mike Khosraviani, Robert Kwong, Manish Motwani, Chitresh Narasimhaiah, Sam J. Nicolino, Tooru Ozeki, Gary Peterson, Chris Salzmann, Nasser Shayesteh, Jeffrey Whitman, Pak Wong
"... Abstract- The next generation UltraSPARC-I CPU represents a significant step forward in processor performance at the cost of increased design complexity. Added complexity increases the risks in achieving functionally correct first silicon. Existing design verification techniques were supplemented by ..."
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by applying emulation to obtain an early look at functionality. Discussed are the goals, methods and results of the UltraSPARC-I emulation. I.

Shade: A Fast Instruction-Set Simulator for Execution Profiling

by Bob Cmelik , David Keppel , 1994
"... Tracing tools are used widely to help analyze, design, and tune both hardware and software systems. This paper describes a tool called Shade which combines efficient instruction-set simulation with a flexible, extensible trace generation capability. Efficiency is achieved by dynamically compiling an ..."
Abstract - Cited by 383 (2 self) - Add to MetaCart
implementations run on SPARC systems and simulate the SPARC (Versions 8 and 9) and MIPS I instruction sets. This paper describes the capabilities, design, implementation, and performance of Shade, and discusses instruction set emulation in general.

UltraSPARC Processor Emulation Verification: Getting HW/SW right the first time Jai Kumar Verification Technologist

by Sun Microsystems , 2007
"... With reduced time-to-market and highly competitive marketplace, it is now important, more than ever, to get the product right the first time! And this is no different for latest generation CoolThreads UltraSPARC T1 processor. The UltraSPARC T1 processor represents one of the highest throughput and m ..."
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With reduced time-to-market and highly competitive marketplace, it is now important, more than ever, to get the product right the first time! And this is no different for latest generation CoolThreads UltraSPARC T1 processor. The UltraSPARC T1 processor represents one of the highest throughput

Emulating Operating System Calls in Retargetable ISA Simulators

by Marcus Bartholomeu, Sandro Rigo, Rodolfo Azevedo, Guido Araujo , 2003
"... In this paper, we propose a method that enables operating system calls from inside architecture simulators. The proposed framework provides support to le I/O and dynamic memory systems, and can be incorporated into any ISA simulator, at the instruction or cycle-accurate levels. It enables calls ..."
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are redirected to the host console. This framework was tested in ISA simulators synthesized from models written in the ArchC Architecture Description Language, but it can be incorporated into any ADL or hand-coded simulator. Instruction and cycle-accurate models, for both MIPS I and SPARC V8 architectures

Implementation of BEE: a Real-time Large-scale Hardware Emulation Engine

by Chen Chang, Kimmo Kuusilinna, Brian Richards, Robert W. Brodersen - International Symposium on Field Programmable Gate Arrays (FPGA
"... This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific Integrated Circuits) equivalent gates. Attainable system operation frequency can exceed 60 MHz ..."
Abstract - Cited by 21 (3 self) - Add to MetaCart
-speed interconnect architecture and large external I/O bandwidth, the emulator excels in prototyping real-time systems that have strict timing, logic capacity, and data rate requirements. Our development efforts are guided by such ongoing projects as ultra-wide band (UWB) and multi-channel-multi-antenna (MCMA) radio

ProtoFlex: FPGA-accelerated Hybrid Functional Simulation

by Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai , 2007
"... Abstract. PROTOFLEX is an FPGA-accelerated hybrid simulation/emulation platform designed to support large-scale multiprocessor hardware and software research. Unlike prior attempts at FPGA multiprocessor system emulators, PROTOFLEX emulates full-system fidelity—i.e., runs stock commercial operating ..."
Abstract - Cited by 11 (1 self) - Add to MetaCart
. By working in concert with existing full-system simulators, transplanting avoids the costly and unnecessary construction of the entire target system in FPGA. We report preliminary findings from a working hybrid PROTOFLEX emulator of an UltraSPARC workstation running Solaris 8. We have also started developing

The RAW Benchmark Suite: Computation Structures for General Purpose Computing

by Jonathan Babb , Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Taylor, Jang Kim, Srikrishna Devabhaktuni, Anant Agarwal - IN IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES , 1997
"... The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut of algorithms found in general purpose computing, including sorting, matrix operations, and graph algorithms. The suite inc ..."
Abstract - Cited by 46 (9 self) - Add to MetaCart
). Because the virtual wires techniques abstract away machine-level details like FPGA capacity and interconnect, our hardware target for this system is an abstract reconfigurable logic fabric with memorymapped host I/O. We report initial speeds in the range of 2X to 1800X faster than a 2.82 SPECint95 Sparc

Implementation Aspects of a SPARC V9 Complete Machine Simulator

by Bill Clarke, Adam Czezowski, Peter Strazdins - ACSAC-2002, the Australasian Computer Systems Architecture Conference , 2002
"... In this paper we present work in progress in the development of a complete machine simulator for the UltraSPARC, an implementation of the SPARC V9 architecture. The complexity of the UltraSPARC ISA presents many challenges in developing a reliable and yet reasonably efficient implementation of such ..."
Abstract - Cited by 10 (7 self) - Add to MetaCart
In this paper we present work in progress in the development of a complete machine simulator for the UltraSPARC, an implementation of the SPARC V9 architecture. The complexity of the UltraSPARC ISA presents many challenges in developing a reliable and yet reasonably efficient implementation

Importance of CAD Tools and Methodologies in High Speed CPU Design

by Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto
"... Abstract- Design methodologies and CAD for “Emotion Engine ” LSI are presented with emphasis on practical aspects of verification and timing closure. A combination of simulation, emulation and formal verification ensured the functional first silicon for system evaluation. In order to control wire de ..."
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and application-like test. For example, it would have taken 571 days for whole EE simulation (740Mcycles) if one UltraSPARC-II class workstation had been used.

I. Computing Methodologies

by Chen Chang, Kimmo Kuusilinna, Brian Richards, Robert W. Brodersen
"... This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific Integrated Circuits) equivalent gates. Attainable system operation frequency can exceed 60 MHz ..."
Abstract - Add to MetaCart
-speed interconnect architecture and large external I/O bandwidth, the emulator excels in prototyping real-time systems that have strict timing, logic capacity, and data rate requirements. Our development efforts are guided by such ongoing projects as ultra-wide band (UWB) and multi-channelmulti-antenna (MCMA) radio
Results 1 - 10 of 28