### Table 7: The role of software and other methods in reducing complexity

"... In PAGE 21: ...2 Managing complexity If we now review the design decisions that were made for the case-study we see how the approach has tended to reduce or control the complexity inherent in the application task. Table7 lists some of... ..."

### Table 1. Transition system sizes when using the RM-Method n apparent complexity algorithmic complexity reduced complexity

"... In PAGE 25: ... This can be achieved by processing the system according to the structure indicated below, where the Ii denote the exact interface speci cations presented in Fig. 7: (z }| { RkP1kB1 kI1 z }| { P2kB2 kI2 : : : kIn?1 z }| { PnkBn)hftk1; : : : ; tkngi Table1 summarises a quantitative evaluation of the e ect of our method by means of the Aldebaran Veri cation Tool [Fer88]. It displays the size of the global state graph (its apparent complexity), the size of the maximal transition system constructed during stepwise minimisation when exploiting exact interface speci- cations (its algorithmic complexity), and the size of the minimised global state graph (its reduced complexity).... ..."

### Table 5.1 : Arithmetic complexity per symbol detection in the Reference and Reduced Complexity DS-CDMA RAKE receivers employing BPSK signaling

### Table 1. Arithmetic complexity per symbol detection in the Reference and Reduced Complexity DS-CDMA RAKE receivers employing BPSK signaling.

### Table 3. FPGA implementation of Reference and Reduced Complexity architectures for the DS-CDMA downlink RAKE receiver. Type Bits Area

"... In PAGE 10: ... The dynamic power consump- tion was obtained after calculating the difference of the overall design power consumption and the queiscent power (225 mW) of the FPGA. In Table3 , the results of implementation of the reference and reduced complexity architectures have been reported. The area shown in the table is represented in FGPA slices as well as the per- centage occupancy in the FPGA, with the available area being 10752 slices in a Virtex-II FPGA.... ..."

### Table 1 summarises a quantitative evaluation of the e ect of our method by means of the Aldebaran Veri cation Tool [Fer88]. It displays the size of the global state graph (its apparent complexity), the size of the maximal transition system constructed during stepwise minimisation when exploiting exact interface speci- cations (its algorithmic complexity), and the size of the minimised global state graph (its reduced complexity). It is worth mentioning that the method, which works just by stepwise composition and minimisation of components, encounters transition systems that are even larger than the global state graph (cf. Table 2). This stresses the importance of interface speci cations for automatic proof tech- niques. Software designers should always provide these speci cations as part of the implementation. We believe that besides enabling automatic veri cation, this

"... In PAGE 25: ...ig. 7. Exact interface speci cations. Table1 . Transition system sizes when using the RM-Method n apparent complexity algorithmic complexity reduced complexity states trans.... ..."

### Table 4-1: Arithmetic operations per sample [Ling85] The complexity of the LSL is about half that of the RLS for the SUI-2 channel and for the SUI-3 channel the complexity of the LSL is nearly 3 times lower than RLS. Thus for MMDS systems it is clear that an RLS algorithm with a linearly increasing complexity (e.g. LSL) offers the best performance/complexity trade-off. In this case LSL offers similar performance to RLS, but with greatly reduced complexity. The complexity of the LMS is very low for both channels considered. However, despite the advantage of the low computational complexity, the LMS algorithm does not offer an acceptable convergence rate as seen in Fig. 4-2 and in Fig. 4-4.

2002

"... In PAGE 11: ... 4-5: Probability of symbol error for channel SUI-3: a) matched filter bound for AWGN channel, b) RLSDFE, c) LSLDFE, d) LMSDFE and e) LMSLE 60 Fig. 4-6: Complexity: a) LMS, b) LSL and c) standard RLS (for equations see Table4 -1) 61 Fig. 5-1: SDMA/TDMA system model 66 Fig.... In PAGE 77: ...Equalization and Space-Time Processing for Fixed Broadband Wireless Access Systems Chapter 4 - Equalization Requirement Study for Single Antenna MMDS FBWA Systems 61 Hence from Fig. 4-6 and Table4 -1 the complexity for equalizers with a total of 15 taps in the SUI-2 channel is 630 operations per output for the RLS, 378 operations per output for the LSL and 31 operations per output for the LMS algorithms. The equalizers appropriate for the SUI-3 channel (i.... In PAGE 77: ... 0 5 10 15 20 25 30 0 500 1000 1500 2000 2500 total number of taps num be r o f o per at i o ns pe r o u t put 31 57 378 630 2086 717 Fig. 4-6: Complexity: a) LMS, b) LSL and c) standard RLS (for equations see Table4 -1) ... ..."

### TABLE I STEPS TO OBTAIN THE DIAGONAL MIMO SYSTEM IN CASE OF CSI AT THE TRANSMITTER.

2004

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