### Table 4: Results of performance-driven clustering

"... In PAGE 5: ... For example, picking up a seed node with high probability of reducing depth will reduce the depth than randomly selecting a seed, and so forth. Results of the performance-driven clustering algorithm, called PackGen-delay, are provided in Table4 . QuickWorks is set to minimize delay during logic optimization.... ..."

### Table IV: Comparison of routing results of statistical density (A) Performance-Driven [14] (B) Routability-Driven [14] (C) Proposed Balanced Density with

2005

Cited by 3

### Table 5 shows capacitance extraction results obtained with the Raphael 3-D eld solver from TMA / Avant!, for an isolated conductor (i) with or without ll insertion in empty regions of adjacent layers, and (ii) with or without same-layer neighbor conductors.17 The simulation shows that ignoring the possibility of metal ll can result in underestimation of total line capacitance by more than 50%. This can in turn lead to inaccurate RCX, delay calculation, and timing analysis results. We conclude that the presence or absence of ll geometries must be modeled during performance-driven layout optimization. Such modeling must be e cient and \transparent quot;; since there are many iterations through the layout optimization loop, we must be careful with the time complexity of ll insertion and the increases in data volume.

"... In PAGE 29: ... Table5 : Raphael 3-D eld solver results for total capacitance extraction of a single victim conductor. The conductor on layer i is 20 1.... ..."

### Table 5 shows capacitance extraction results obtained with the Raphael 3-D eld solver from TMA / Avant!, for an isolated conductor (i) with or without ll insertion in empty regions of adjacent layers, and (ii) with or without same-layer neighbor conductors.17 The simulation shows that ignoring the possibility of metal ll can result in underestimation of total line capacitance by more than 50%. This can in turn lead to inaccurate RCX, delay calculation, and timing analysis results. We conclude that the presence or absence of ll geometries must be modeled during performance-driven layout optimization. Such modeling must be e cient and \transparent quot;; since there are many iterations through the layout optimization loop, we must be careful with the time complexity of ll insertion and the increases in data volume.

"... In PAGE 29: ... Table5 : Raphael 3-D eld solver results for total capacitance extraction of a single victim conductor. The conductor on layer i is 20 1.... ..."

### Table 5: Iterative performance for Driven Cavity problem e40r3000. ILU(1) converged very slowly, and was terminated before achieving exit criteria. level solution PC formation residual iterations

"... In PAGE 10: ... All the problem can be solved, however, using high-level pre- conditioners. Table5 shows a typical problem, for which the fastest solution time was obtained with ILU(3) preconditioning. This problem can also be solved using high- level ILUT preconditioning, although we found that solution times were slower, with larger amounts of fill required to force convergence.... ..."

### Table 1: Topology e ects on delay. For a net with multiple sources, the delay to a given sink depends on which node drives the net. performance-driven routing algorithms for single source nets may perform poorly, as a topology optimized for one source may result in long interconnect delay when some other source becomes active. Figure 1 presents a pair of routing trees with equal wire length over four nodes. The rst routing tree, optimized for node p1 and has relatively high delay when node p2 drives the net. The second routing tree provides a lower overall maximum delay when all four nodes might be sources or sinks. Delay times with respect to the driving nodes are shown in Table 1. While it has been shown that both the optimal Steiner tree with minimum wirelength and the optimal single source routing tree under the Elmore delay model can be constructed on the Hanan grid[10, 2], the second routing tree, with improved worst-case performance, does not lie completely on the Hanan grid.

1995

Cited by 20

### Table 2: Computed bounds on the average cycle time of consecutive occurrence of transition tRowReq0. The relative error interval is set to 5% and the con dence level is set to 99% during Monte Carlo sampling. straight forward Monte-Carlo sampling it should also be possible to use more sophisticated strati ed and im- portance sampling [Ros90] techniques to reduce the number of random samples needed. In addition, we would like to explore extensions to Petri net models that can model arbitration. We believe this tool is not only useful for architectural exploration and analysis but also may be quite useful if integrated with performance-driven controller synthesis. To do the later, however, we may need to nd multiple TSEs simultaneously and perhaps keeping track of the distribution of TSEs rather than simply their running average. Some of the issues are addressed in a companion paper submitted to this conference [MMB]. References

1999

"... In PAGE 14: ... units. The results are tabulated in Table2 . Since we did not have su cient time to match our modeled delays with the real design we rather not stress the signi cance of the performance trends.... ..."

Cited by 16

### Table 1: Minimum density routing tree statistics. some promise in the sense that there exist examples where this method outperforms the algorithms COMB and COMB ST by a factor of (pn) (see Figure 12); we believe that PEEL can be shown to yield worst-case density that is within a constant factor of optimal. Indeed, we o er two closely related conjectures: (i) that the minimum density of a spanning tree over net N is at least the minimum of the number of chains or the number of antichains needed to cover N; and (ii) the PEEL algorithm will use at most two times the minimum possible number of chains/antichains that cover N. In conclusion, we have proposed a new spanning and Steiner tree formulation, based on a minimum density criterion. We have also presented several e cient heuristics for constructing low-density span- ning and Steiner trees. We prove that on average the performance of our algorithm is bounded by small constants away from optimal, in terms of both tree cost and density. We also show how our techniques can be used to unify the new density criterion with previous \performance-driven quot; interconnection 15

1992

### Table 5 Software refactoring summary Approach/technique Source code refactoring

2005

"... In PAGE 6: ...able 4 Software patterns summary ............................................................................................................. 25 Table5 Software refactoring summary .... ..."