"... In PAGE 5: ... We first initialized the combinatorial blocks between registers us- ing the algorithm of [1] and then applied our algorithm to reduce the clock period of the design. The synthesis job took several sec- onds of CPU time on a Sparc Ultra-10 workstation and the synthe- sis results for timing optimization are summarized in Table2 . The proposed transformations across register boundaries significantly re- duced the cycle time of the circuits generated using the algorithm... In PAGE 5: ... The proposed transformations across register boundaries significantly re- duced the cycle time of the circuits generated using the algorithm in [1]. We also compare, in Table2... In PAGE 6: ... The power of operation duplicate and its combination with operations forward and backward is reflected in these design examples and results. The advantage of using signal representation guided carry-save transformations across register boundaries is clearest for clock pe- riod optimization, as shown in Table2 . However, our algorithm is also capable of producing circuit implementations having relatively small area.... ..."

"... In PAGE 5: ... We first initialized the combinatorial blocks between registers us- ing the algorithm of [1] and then applied our algorithm to reduce the clock period of the design. The synthesis job took several sec- onds of CPU time on a Sparc Ultra-10 workstation and the synthe- sis results for timing optimization are summarized in Table2 . The proposed transformations across register boundaries significantly re- duced the cycle time of the circuits generated using the algorithm... In PAGE 5: ... The proposed transformations across register boundaries significantly re- duced the cycle time of the circuits generated using the algorithm in [1]. We also compare, in Table2... In PAGE 6: ... The power of operation duplicate and its combination with operations forward and backward is reflected in these design examples and results. The advantage of using signal representation guided carry-save transformations across register boundaries is clearest for clock pe- riod optimization, as shown in Table2 . However, our algorithm is also capable of producing circuit implementations having relatively small area.... ..."

"... In PAGE 12: ...able 6: Estimated execution times for experiment 2. ..................................................... 60 Table7 : Actual execution times for optimal configuration.... In PAGE 73: ...00x8 0.91 3.31 6.64 These (and other) experiments suggest that a concrete configuration similar to the abstract configuration of experiment 2 would be near optimal. Table7 shows the execution times for the program with concrete components. Table 7: Actual execution times for optimal configuration ... ..."

"... In PAGE 15: ...Table 2: Compilation Times of the Optimizing Compiler Table2 describes the compilation time for the same benchmarks, although no e ort has been spent making the compiler fast at this point. The table depicts the time of the three optimization phases (the rst phase containing the parsing and the normalization as well).... ..."

"... In PAGE 5: ...Table 6: Synthesis times (fast mode) 3.3 Results Table5 provides a comparison of the results of syn- thesis of the unpartitioned and functionally partitioned examples, using optimal mode logic synthesis. The Dup column represents the number of duplications for a given example, as described earlier.... In PAGE 5: ... (Only three of the four examples are shown in each table, as the synthesis tool apos;s limitations at the time the experiments were performed prevented com- pletion of some duplicated examples.) Table 6 is identical to Table5 except that it shows results using the fast logic synthesis mode. Finally, Ta- ble 7 shows the size results.... ..."