Results 1 - 10 of 170

FUSE: Front-end user framework for O/S abstraction of hardware accelerators

by Aws Ismail, Lesley Shannon - in Proc. 19th IEEE Symp. FieldProgram. Custom Comput , 2011
"... Abstract—SoCs can be implemented on a single FPGA, offering designers a unique opportunity for Embedded Sys-tems. Instead of defining a fixed architecture early in the design process, the reconfigurable platform allows architec-tural redesign to meet the system’s specific needs. However, the ability ..."
Abstract - Cited by 7 (0 self) - Add to MetaCart
, a framework for HW accelerator abstraction that provides: 1) transparency to the SW designer at the application level; and 2) OS support for easy HW accelerator integration. We illustrate FUSE as an API for an embedded Linux OS with POSIX threads on Xilinx’s MicroBlaze on a Virtex5. For three

Framework for Testing Cloud Platforms and

by William Jenkins, Sergiy Vilkomir, Puneet Sharma, George Pirocanac
"... Abstract — Cloud computing, which is a relatively new approach to distributed computing, uses cloud infrastructures that automatically scale to support an application's hardware requirements, and therefore, must have high reliability in order to meet user expectations. To achieve a high level o ..."
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framework is presented, which accelerates testing and provides for parallel development of test cases. This framework is a cloud application, which contains plugins for testing APIs of cloud platforms. A prototype framework for testing Google App Engine has been created to show demonstrated applicability

A framework for flexible, hardware-accelerated, and high-quality volume rendering

by Christoph Berger - In Proceedings of the Central European Seminar on Computer Graphics , 2003
"... Through the invention of new rendering algorithms and an enormous development of graphics hardware in the past it is now possible to perform interactive hardwareaccelerated high quality volume rendering as well as isosurface reconstruction on low cost standard PC graphics hardware. In this paper we ..."
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introduce a flexible framework that supports the most common graphics adapters without additional need of setup as well as several vendor-dependent OpenGL-extensions like pixel-, texture- and fragmentshader. Additionally the framework integrates most recent presented rendering techniques which significantly

HyperCheck: A Hardware-Assisted Integrity Monitor

by Jiang Wang, Angelos Stavrou, Anup Ghosh
"... Abstract. Over the past few years, virtualization has been employed to environments ranging from densely populated cloud computing clusters to home desktop computers. Security researchers embraced virtual machine monitors (VMMs) as a new mechanism to guarantee deep isolation of untrusted software co ..."
Abstract - Cited by 33 (8 self) - Add to MetaCart
components. Unfortunately, their widespread adoption promoted VMMs as a prime target for attackers. In this paper, we present HyperCheck, a hardware-assisted tampering detection framework designed to protect the integrity of VMMs and, for some classes of attacks, the underlying operating system (OS). Hyper

A Case for OS-Friendly Hardware Accelerators

by Huy Vo, Yunsup Lee, Andrew Waterman, Krste Asanović
"... Modern SoCs make extensive use of specialized hardware accelerators to meet the demanding energy-efficiency requirements of demanding applications, such as computer graphics and video encoding/decoding. Unfortunately, the state of the art is a sea of heterogeneous fixed-function processing units wir ..."
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overhead that reduces achievable speedups on a wide range of applications. We propose that accelerators should adopt a more standardized OS-friendly interface, to ease integration and improve performance on a wider range of code. Our framework standardizes the host-accelerator communication interface

Energy-Efficient Hardware Acceleration through Computing in the Memory

by Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri
"... Abstract—Energy-efficiency has emerged as a major barrier to performance scalability for modern processors. We note that significant part of processor’s energy requirement is contributed by processor-memory communication. To address the energy issue in processors, we propose a novel hardware acceler ..."
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uses a memory block as its local memory. The proposed framework provides some unique advantages for hardware acceleration compared to conventional accelerators: 1) memory array provides large set of parallel resources with high bandwidth, which can be configured to perform computing in spatio

Automated Extraction of Hardware Accelerators Via an Intelligent

by Michael F. Dossis, Michael F. Dossis
"... doi:10.4156/ijiip.vol1. issue2.2 Due to the increased complexity of modern embedded applications and integrated circuits there has been a long effort for automated techniques and tools to automatically produce correct hardware and systems from high-level, abstract and executable specifications writt ..."
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framework for verified and correct hardware accelerators. The IKBS design framework transforms a number of Prolog predicate facts into a number of verified hardware modules, via its inference engine’s logic rules. The predicate facts are produced automatically via a front-end compiler and directly from high

1 Beyond Triangles: A Simple Framework For Hardware-Accelerated Non-Triangular Primitives

by Walter Mundt, Sumanta Pattanaik, Erik Reinhard
"... Abstract — Recent advances in the capabilities of graphics hardware have allowed the development of various techniques for directly rendering non-triangular primitives on graphics hardware in real time. We introduce an simple, efficient framework for integrating arbitrary ray-casted primitives into ..."
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Abstract — Recent advances in the capabilities of graphics hardware have allowed the development of various techniques for directly rendering non-triangular primitives on graphics hardware in real time. We introduce an simple, efficient framework for integrating arbitrary ray-casted primitives

Mushi: Toward multiple level security cloud with strong hardware level isolation

by Ning Zhang, Ming Li, Wenjing Lou, Y. Thomas Hou - In MILCOM , 2012
"... Abstract—Multiple Level Security (MLS) has always been a center of focus since the usage of computers in military and intelligence systems. Extensive studies have been done on how to utilize virtualization technologies to provide multiple level secured execution in the cloud, yet the general assumpt ..."
Abstract - Cited by 2 (1 self) - Add to MetaCart
Security cloud with strong Hardware level Isolation (MUSHI), a novel framework that can provide hardware level isolation and protection to individual guest virtual machine (VM) execution. With MUSHI, a user can maintain confidentiality and integrity of her VM in a multicore environment even in the presence

HARDWARE-IN-THE-LOOP SIMULATION FOR AUTOMATED BENCHMARKING OF CLOUD INFRASTRUCTURES

by C. Laroque, J. Himmelspach, R. Pasupathy, O. Rose, A. M. Uhrmacher, Qi Liu, Marcio A. Silva, Michael R. Hines, Dilma Da Silva
"... To address the challenge of automated performance benchmarking in virtualized cloud infrastructures, an extensible and adaptable framework called CloudBench has been developed to conduct scalable, controllable, and repeatable experiments in such environments. This paper presents the hardware-in-the- ..."
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To address the challenge of automated performance benchmarking in virtualized cloud infrastructures, an extensible and adaptable framework called CloudBench has been developed to conduct scalable, controllable, and repeatable experiments in such environments. This paper presents the hardware
Results 1 - 10 of 170